a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
190 lines
3.4 KiB
Plaintext
190 lines
3.4 KiB
Plaintext
test compile precise-output
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target s390x
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function %foo() {
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block0:
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return
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}
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; block0:
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; br %r14
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function %stack_limit_leaf_zero(i64 stack_limit) {
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block0(v0: i64):
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return
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}
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; block0:
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; br %r14
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function %stack_limit_gv_leaf_zero(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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block0(v0: i64):
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return
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}
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; block0:
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; br %r14
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function %stack_limit_call_zero(i64 stack_limit) {
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fn0 = %foo()
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block0(v0: i64):
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call fn0()
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return
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}
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; clgrtle %r15, %r2
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; bras %r1, 12 ; data %foo + 0 ; lg %r4, 0(%r1)
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; basr %r14, %r4
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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function %stack_limit_gv_call_zero(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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fn0 = %foo()
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block0(v0: i64):
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call fn0()
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return
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}
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; lg %r1, 0(%r2)
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; lg %r1, 4(%r1)
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; clgrtle %r15, %r1
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; bras %r1, 12 ; data %foo + 0 ; lg %r4, 0(%r1)
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; basr %r14, %r4
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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function %stack_limit(i64 stack_limit) {
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ss0 = explicit_slot 168
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block0(v0: i64):
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return
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}
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; la %r1, 168(%r2)
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; clgrtle %r15, %r1
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; aghi %r15, -168
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; block0:
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; aghi %r15, 168
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; br %r14
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function %large_stack_limit(i64 stack_limit) {
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ss0 = explicit_slot 400000
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block0(v0: i64):
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return
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}
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; clgrtle %r15, %r2
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; lay %r1, 400000(%r2)
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; clgrtle %r15, %r1
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; agfi %r15, -400000
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; block0:
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; agfi %r15, 400000
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; br %r14
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function %huge_stack_limit(i64 stack_limit) {
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ss0 = explicit_slot 4000000
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block0(v0: i64):
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return
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}
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; clgrtle %r15, %r2
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; lgr %r1, %r2
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; algfi %r1, 4000000
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; clgrtle %r15, %r1
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; agfi %r15, -4000000
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; block0:
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; agfi %r15, 4000000
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; br %r14
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function %limit_preamble(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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ss0 = explicit_slot 20
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block0(v0: i64):
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return
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}
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; lg %r1, 0(%r2)
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; lg %r1, 4(%r1)
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; la %r1, 24(%r1)
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; clgrtle %r15, %r1
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; aghi %r15, -24
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; block0:
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; aghi %r15, 24
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; br %r14
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function %limit_preamble_large(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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ss0 = explicit_slot 400000
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block0(v0: i64):
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return
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}
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; lg %r1, 0(%r2)
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; lg %r1, 4(%r1)
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; clgrtle %r15, %r1
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; lay %r1, 400000(%r1)
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; clgrtle %r15, %r1
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; agfi %r15, -400000
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; block0:
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; agfi %r15, 400000
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; br %r14
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function %limit_preamble_huge(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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ss0 = explicit_slot 4000000
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block0(v0: i64):
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return
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}
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; lg %r1, 0(%r2)
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; lg %r1, 4(%r1)
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; clgrtle %r15, %r1
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; algfi %r1, 4000000
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; clgrtle %r15, %r1
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; agfi %r15, -4000000
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; block0:
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; agfi %r15, 4000000
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; br %r14
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function %limit_preamble_huge_offset(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+1000000
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stack_limit = gv1
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ss0 = explicit_slot 20
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block0(v0: i64):
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return
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}
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; lgfi %r1, 1000000 ; lg %r1, 0(%r1,%r2)
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; la %r1, 24(%r1)
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; clgrtle %r15, %r1
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; aghi %r15, -24
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; block0:
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; aghi %r15, 24
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; br %r14
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