a916788ab4
This fixes two problems: minimum symbol alignment for the LARL instruction, and alignment requirements for LRL/LGRL etc. The first problem is that the LARL instruction used to load a symbol address (PC relative) requires that the target symbol is at least 2-byte aligned. This is always guaranteed for code symbols (all instructions must be 2-aligned anyway), but not necessarily for data symbols. Other s390x compilers fix this problem by ensuring that all global symbols are always emitted with a minimum 2-byte alignment. This patch introduces an equivalent mechanism for cranelift: - Add a symbol_alignment routine to TargetIsa, similar to the existing code_section_alignment routine. - Respect symbol_alignment as minimum alignment for all symbols emitted in the object backend (code and data). The second problem is that PC-relative instructions that directly *access* data (like LRL/LGRL, STRL/STGRL etc.) not only have the 2-byte requirement like LARL, but actually require that their memory operand is *naturally* aligned (i.e. alignment is at least the size of the access). This property (natural alignment for memory accesses) is supposed to be provided by the "aligned" flag in MemFlags; however, this is not implemented correctly at the moment. To fix this, this patch: - Only emits PC-relative memory access instructions if the "aligned" flag is set in the associated MemFlags. - Fixes a bug in emit_small_memory_copy and emit_small_memset which currently set the aligned flag unconditionally, ignoring the actual alignment info passed by their caller. Tested with wasmtime and cg_clif.
137 lines
2.2 KiB
Plaintext
137 lines
2.2 KiB
Plaintext
test compile precise-output
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target s390x
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function %atomic_store_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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atomic_store.i64 little v0, v1
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return
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}
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; block0:
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; strvg %r2, 0(%r3)
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; bcr 14, 0
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; br %r14
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function %atomic_store_i64_sym(i64) {
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gv0 = symbol colocated %sym
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block0(v0: i64):
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v1 = symbol_value.i64 gv0
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atomic_store.i64 aligned little v0, v1
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return
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}
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; block0:
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; larl %r1, %sym + 0 ; strvg %r2, 0(%r1)
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; bcr 14, 0
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; br %r14
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function %atomic_store_imm_i64(i64) {
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block0(v0: i64):
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v1 = iconst.i64 12345
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atomic_store.i64 little v1, v0
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return
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}
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; block0:
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; lghi %r4, 12345
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; strvg %r4, 0(%r2)
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; bcr 14, 0
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; br %r14
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function %atomic_store_i32(i32, i64) {
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block0(v0: i32, v1: i64):
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atomic_store.i32 little v0, v1
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return
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}
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; block0:
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; strv %r2, 0(%r3)
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; bcr 14, 0
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; br %r14
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function %atomic_store_i32_sym(i32) {
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gv0 = symbol colocated %sym
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block0(v0: i32):
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v1 = symbol_value.i64 gv0
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atomic_store.i32 aligned little v0, v1
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return
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}
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; block0:
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; larl %r1, %sym + 0 ; strv %r2, 0(%r1)
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; bcr 14, 0
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; br %r14
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function %atomic_store_imm_i32(i64) {
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block0(v0: i64):
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v1 = iconst.i32 12345
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atomic_store.i32 little v1, v0
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return
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}
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; block0:
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; lhi %r4, 12345
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; strv %r4, 0(%r2)
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; bcr 14, 0
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; br %r14
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function %atomic_store_i16(i16, i64) {
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block0(v0: i16, v1: i64):
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atomic_store.i16 little v0, v1
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return
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}
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; block0:
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; strvh %r2, 0(%r3)
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; bcr 14, 0
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; br %r14
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function %atomic_store_i16_sym(i16) {
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gv0 = symbol colocated %sym
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block0(v0: i16):
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v1 = symbol_value.i64 gv0
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atomic_store.i16 aligned little v0, v1
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return
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}
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; block0:
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; larl %r1, %sym + 0 ; strvh %r2, 0(%r1)
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; bcr 14, 0
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; br %r14
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function %atomic_store_imm_i16(i64) {
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block0(v0: i64):
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v1 = iconst.i16 12345
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atomic_store.i16 little v1, v0
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return
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}
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; block0:
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; mvhhi 0(%r2), 14640
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; bcr 14, 0
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; br %r14
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function %atomic_store_i8(i8, i64) {
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block0(v0: i8, v1: i64):
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atomic_store.i8 little v0, v1
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return
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}
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; block0:
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; stc %r2, 0(%r3)
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; bcr 14, 0
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; br %r14
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function %atomic_store_imm_i8(i64) {
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block0(v0: i64):
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v1 = iconst.i8 123
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atomic_store.i8 little v1, v0
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return
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}
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; block0:
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; mvi 0(%r2), 123
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; bcr 14, 0
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; br %r14
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