26c78c06ef
PR #3131 fixed the failing builds by allowing this field to be dead. After looking at it further the field is not being used and can be removedi completely.
88 lines
3.2 KiB
Rust
88 lines
3.2 KiB
Rust
use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::types::{ReferenceType, VectorType};
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use crate::shared::types::Bool::B1;
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use crate::shared::types::Float::{F32, F64};
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use crate::shared::types::Int::{I16, I32, I64, I8};
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use crate::shared::types::Reference::{R32, R64};
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use crate::shared::Definitions as SharedDefinitions;
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mod encodings;
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mod instructions;
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mod legalize;
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mod opcodes;
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mod recipes;
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mod registers;
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pub(crate) mod settings;
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pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = settings::define(&shared_defs.settings);
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let regs = registers::define();
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let inst_group = instructions::define(
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&mut shared_defs.all_instructions,
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&shared_defs.formats,
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&shared_defs.imm,
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&shared_defs.entities,
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);
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legalize::define(shared_defs, &inst_group);
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// CPU modes for 32-bit and 64-bit operations.
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let mut x86_64 = CpuMode::new("I64");
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let mut x86_32 = CpuMode::new("I32");
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let expand_flags = shared_defs.transform_groups.by_name("expand_flags");
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let x86_widen = shared_defs.transform_groups.by_name("x86_widen");
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let x86_narrow = shared_defs.transform_groups.by_name("x86_narrow");
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let x86_narrow_avx = shared_defs.transform_groups.by_name("x86_narrow_avx");
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let x86_expand = shared_defs.transform_groups.by_name("x86_expand");
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x86_32.legalize_monomorphic(expand_flags);
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x86_32.legalize_default(x86_narrow);
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x86_32.legalize_type(B1, expand_flags);
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x86_32.legalize_type(I8, x86_widen);
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x86_32.legalize_type(I16, x86_widen);
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x86_32.legalize_type(I32, x86_expand);
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x86_32.legalize_value_type(ReferenceType(R32), x86_expand);
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x86_32.legalize_type(F32, x86_expand);
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x86_32.legalize_type(F64, x86_expand);
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x86_32.legalize_value_type(VectorType::new(I32.into(), 4), x86_narrow_avx);
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x86_32.legalize_value_type(VectorType::new(I64.into(), 2), x86_narrow_avx);
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x86_32.legalize_value_type(VectorType::new(F32.into(), 4), x86_narrow_avx);
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x86_64.legalize_monomorphic(expand_flags);
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x86_64.legalize_default(x86_narrow);
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x86_64.legalize_type(B1, expand_flags);
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x86_64.legalize_type(I8, x86_widen);
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x86_64.legalize_type(I16, x86_widen);
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x86_64.legalize_type(I32, x86_expand);
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x86_64.legalize_type(I64, x86_expand);
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x86_64.legalize_value_type(ReferenceType(R64), x86_expand);
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x86_64.legalize_type(F32, x86_expand);
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x86_64.legalize_type(F64, x86_expand);
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x86_64.legalize_value_type(VectorType::new(I32.into(), 4), x86_narrow_avx);
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x86_64.legalize_value_type(VectorType::new(I64.into(), 2), x86_narrow_avx);
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x86_64.legalize_value_type(VectorType::new(F32.into(), 4), x86_narrow_avx);
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let recipes = recipes::define(shared_defs, &settings, ®s);
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let encodings = encodings::define(shared_defs, &settings, &inst_group, &recipes);
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x86_32.set_encodings(encodings.enc32);
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x86_64.set_encodings(encodings.enc64);
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let encodings_predicates = encodings.inst_pred_reg.extract();
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let recipes = encodings.recipes;
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let cpu_modes = vec![x86_64, x86_32];
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TargetIsa::new(
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"x86",
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settings,
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regs,
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recipes,
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cpu_modes,
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encodings_predicates,
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)
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}
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