This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
273 lines
11 KiB
Rust
273 lines
11 KiB
Rust
//! System V ABI unwind information.
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use crate::isa::unwind::UnwindInst;
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use crate::machinst::Reg;
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use crate::result::CodegenResult;
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use crate::{binemit::CodeOffset, CodegenError};
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use alloc::vec::Vec;
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use gimli::write::{Address, FrameDescriptionEntry};
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#[cfg(feature = "enable-serde")]
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use serde::{Deserialize, Serialize};
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type Register = u16;
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/// Enumerate the errors possible in mapping Cranelift registers to their DWARF equivalent.
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#[allow(missing_docs)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum RegisterMappingError {
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MissingBank,
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UnsupportedArchitecture,
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UnsupportedRegisterBank(&'static str),
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}
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// This is manually implementing Error and Display instead of using thiserror to reduce the amount
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// of dependencies used by Cranelift.
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impl std::error::Error for RegisterMappingError {}
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impl std::fmt::Display for RegisterMappingError {
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fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
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match self {
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RegisterMappingError::MissingBank => write!(f, "unable to find bank for register info"),
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RegisterMappingError::UnsupportedArchitecture => write!(
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f,
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"register mapping is currently only implemented for x86_64"
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),
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RegisterMappingError::UnsupportedRegisterBank(bank) => {
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write!(f, "unsupported register bank: {}", bank)
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}
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}
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}
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}
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// This mirrors gimli's CallFrameInstruction, but is serializable
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// This excludes CfaExpression, Expression, ValExpression due to
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// https://github.com/gimli-rs/gimli/issues/513.
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// TODO: if gimli ever adds serialization support, remove this type
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#[derive(Clone, Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
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pub(crate) enum CallFrameInstruction {
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Cfa(Register, i32),
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CfaRegister(Register),
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CfaOffset(i32),
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Restore(Register),
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Undefined(Register),
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SameValue(Register),
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Offset(Register, i32),
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ValOffset(Register, i32),
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Register(Register, Register),
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RememberState,
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RestoreState,
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ArgsSize(u32),
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/// Enables or disables pointer authentication on aarch64 platforms post ARMv8.3. This
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/// particular item maps to gimli::ValExpression(RA_SIGN_STATE, lit0/lit1).
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Aarch64SetPointerAuth {
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return_addresses: bool,
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},
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}
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impl From<gimli::write::CallFrameInstruction> for CallFrameInstruction {
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fn from(cfi: gimli::write::CallFrameInstruction) -> Self {
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use gimli::write::CallFrameInstruction;
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match cfi {
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CallFrameInstruction::Cfa(reg, offset) => Self::Cfa(reg.0, offset),
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CallFrameInstruction::CfaRegister(reg) => Self::CfaRegister(reg.0),
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CallFrameInstruction::CfaOffset(offset) => Self::CfaOffset(offset),
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CallFrameInstruction::Restore(reg) => Self::Restore(reg.0),
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CallFrameInstruction::Undefined(reg) => Self::Undefined(reg.0),
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CallFrameInstruction::SameValue(reg) => Self::SameValue(reg.0),
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CallFrameInstruction::Offset(reg, offset) => Self::Offset(reg.0, offset),
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CallFrameInstruction::ValOffset(reg, offset) => Self::ValOffset(reg.0, offset),
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CallFrameInstruction::Register(reg1, reg2) => Self::Register(reg1.0, reg2.0),
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CallFrameInstruction::RememberState => Self::RememberState,
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CallFrameInstruction::RestoreState => Self::RestoreState,
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CallFrameInstruction::ArgsSize(size) => Self::ArgsSize(size),
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_ => {
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// Cranelift's unwind support does not generate `CallFrameInstruction`s with
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// Expression at this moment, and it is not trivial to
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// serialize such instructions.
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panic!("CallFrameInstruction with Expression not supported");
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}
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}
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}
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}
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impl Into<gimli::write::CallFrameInstruction> for CallFrameInstruction {
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fn into(self) -> gimli::write::CallFrameInstruction {
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use gimli::{write::CallFrameInstruction, write::Expression, Register};
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match self {
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Self::Cfa(reg, offset) => CallFrameInstruction::Cfa(Register(reg), offset),
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Self::CfaRegister(reg) => CallFrameInstruction::CfaRegister(Register(reg)),
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Self::CfaOffset(offset) => CallFrameInstruction::CfaOffset(offset),
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Self::Restore(reg) => CallFrameInstruction::Restore(Register(reg)),
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Self::Undefined(reg) => CallFrameInstruction::Undefined(Register(reg)),
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Self::SameValue(reg) => CallFrameInstruction::SameValue(Register(reg)),
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Self::Offset(reg, offset) => CallFrameInstruction::Offset(Register(reg), offset),
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Self::ValOffset(reg, offset) => CallFrameInstruction::ValOffset(Register(reg), offset),
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Self::Register(reg1, reg2) => {
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CallFrameInstruction::Register(Register(reg1), Register(reg2))
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}
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Self::RememberState => CallFrameInstruction::RememberState,
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Self::RestoreState => CallFrameInstruction::RestoreState,
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Self::ArgsSize(size) => CallFrameInstruction::ArgsSize(size),
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Self::Aarch64SetPointerAuth { return_addresses } => {
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// To enable pointer authentication for return addresses in dwarf directives, we
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// use a small dwarf expression that sets the value of the pseudo-register
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// RA_SIGN_STATE (RA stands for return address) to 0 or 1. This behavior is
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// documented in
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// https://github.com/ARM-software/abi-aa/blob/master/aadwarf64/aadwarf64.rst#41dwarf-register-names.
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let mut expr = Expression::new();
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expr.op(if return_addresses {
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gimli::DW_OP_lit1
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} else {
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gimli::DW_OP_lit0
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});
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const RA_SIGN_STATE: Register = Register(34);
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CallFrameInstruction::ValExpression(RA_SIGN_STATE, expr)
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}
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}
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}
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}
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/// Maps UnwindInfo register to gimli's index space.
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pub(crate) trait RegisterMapper<Reg> {
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/// Maps Reg.
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fn map(&self, reg: Reg) -> Result<Register, RegisterMappingError>;
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/// Gets stack pointer register.
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fn sp(&self) -> Register;
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/// Gets the frame pointer register, if any.
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fn fp(&self) -> Option<Register> {
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None
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}
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/// Gets the link register, if any.
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fn lr(&self) -> Option<Register> {
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None
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}
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/// What is the offset from saved FP to saved LR?
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fn lr_offset(&self) -> Option<u32> {
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None
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}
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}
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/// Represents unwind information for a single System V ABI function.
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///
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/// This representation is not ISA specific.
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#[derive(Clone, Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
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pub struct UnwindInfo {
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instructions: Vec<(u32, CallFrameInstruction)>,
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len: u32,
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}
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pub(crate) fn create_unwind_info_from_insts<MR: RegisterMapper<Reg>>(
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insts: &[(CodeOffset, UnwindInst)],
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code_len: usize,
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mr: &MR,
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) -> CodegenResult<UnwindInfo> {
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let mut instructions = vec![];
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let mut cfa_offset = 0;
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let mut clobber_offset_to_cfa = 0;
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for &(instruction_offset, ref inst) in insts {
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match inst {
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&UnwindInst::PushFrameRegs {
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offset_upward_to_caller_sp,
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} => {
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// Define CFA in terms of current SP (SP changed and we haven't
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// set FP yet).
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instructions.push((
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instruction_offset,
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CallFrameInstruction::CfaOffset(offset_upward_to_caller_sp as i32),
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));
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// Note that we saved the old FP value on the stack. Use of this
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// operation implies that the target defines a FP register.
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instructions.push((
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instruction_offset,
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CallFrameInstruction::Offset(
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mr.fp().unwrap(),
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-(offset_upward_to_caller_sp as i32),
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),
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));
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// If there is a link register on this architecture, note that
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// we saved it as well.
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if let Some(lr) = mr.lr() {
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instructions.push((
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instruction_offset,
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CallFrameInstruction::Offset(
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lr,
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-(offset_upward_to_caller_sp as i32)
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+ mr.lr_offset().expect("LR offset not provided") as i32,
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),
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));
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}
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}
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&UnwindInst::DefineNewFrame {
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offset_upward_to_caller_sp,
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offset_downward_to_clobbers,
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} => {
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// Define CFA in terms of FP. Note that we assume it was already
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// defined correctly in terms of the current SP, and FP has just
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// been set to the current SP, so we do not need to change the
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// offset, only the register. (This is done only if the target
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// defines a frame pointer register.)
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if let Some(fp) = mr.fp() {
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instructions.push((instruction_offset, CallFrameInstruction::CfaRegister(fp)));
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}
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// Record initial CFA offset. This will be used with later
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// StackAlloc calls if we do not have a frame pointer.
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cfa_offset = offset_upward_to_caller_sp;
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// Record distance from CFA downward to clobber area so we can
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// express clobber offsets later in terms of CFA.
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clobber_offset_to_cfa = offset_upward_to_caller_sp + offset_downward_to_clobbers;
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}
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&UnwindInst::StackAlloc { size } => {
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// If we do not use a frame pointer, we need to update the
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// CFA offset whenever the stack pointer changes.
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if mr.fp().is_none() {
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cfa_offset += size;
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instructions.push((
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instruction_offset,
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CallFrameInstruction::CfaOffset(cfa_offset as i32),
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));
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}
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}
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&UnwindInst::SaveReg {
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clobber_offset,
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reg,
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} => {
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let reg = mr
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.map(reg.into())
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.map_err(|e| CodegenError::RegisterMappingError(e))?;
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let off = (clobber_offset as i32) - (clobber_offset_to_cfa as i32);
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instructions.push((instruction_offset, CallFrameInstruction::Offset(reg, off)));
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}
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&UnwindInst::Aarch64SetPointerAuth { return_addresses } => {
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instructions.push((
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instruction_offset,
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CallFrameInstruction::Aarch64SetPointerAuth { return_addresses },
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));
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}
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}
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}
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Ok(UnwindInfo {
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instructions,
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len: code_len as u32,
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})
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}
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impl UnwindInfo {
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/// Converts the unwind information into a `FrameDescriptionEntry`.
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pub fn to_fde(&self, address: Address) -> gimli::write::FrameDescriptionEntry {
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let mut fde = FrameDescriptionEntry::new(address, self.len);
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for (offset, inst) in &self.instructions {
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fde.add_instruction(*offset, inst.clone().into());
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}
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fde
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}
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}
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