Jakob Stoklund Olesen 250c515ba9 Update the register allocator document. ...

- We have a coalescing pass which puts the code in CSSA form.
- We do not have an EBB argument fixup pass. This isn't needed with
  CSSA.

2017-10-20 15:15:22 -07:00

..

.gitignore

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

callex.cton

Use the term "EBB parameter" everywhere.

2017-10-19 16:17:09 -07:00

compare-llvm.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00

conf.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

cton_domain.py

Begin an Intel-specific instruction group.

2017-07-18 11:20:00 -07:00

cton_lexer.py

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

example.c

Update language reference.

2016-01-21 14:25:16 -08:00

example.cton

Add heaps to the Cretonne IL.

2017-08-23 14:15:59 -07:00

heapex-dyn.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

heapex-sm32.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

heapex-sm64.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

index.rst

Start a design document for the Cretonne register allocator.

2016-11-21 17:00:16 -08:00

langref.rst

Remove the definition of "safe".

2017-10-20 11:37:25 -07:00

make.bat

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

Makefile

Add global variables to Cretonne IL.

2017-08-17 14:41:27 -07:00

metaref.rst

Add two new value types: iflags and fflags.

2017-10-12 19:05:24 -07:00

regalloc.rst

Update the register allocator document.

2017-10-20 15:15:22 -07:00

testing.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00