33 lines
794 B
Python
33 lines
794 B
Python
"""
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RISC-V Target
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-------------
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`RISC-V <https://riscv.org/>`_ is an open instruction set architecture
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originally developed at UC Berkeley. It is a RISC-style ISA with either a
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32-bit (RV32I) or 64-bit (RV32I) base instruction set and a number of optional
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extensions:
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RV32M / RV64M
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Integer multiplication and division.
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RV32A / RV64A
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Atomics.
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RV32F / RV64F
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Single-precision IEEE floating point.
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RV32D / RV64D
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Double-precision IEEE floating point.
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RV32G / RV64G
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General purpose instruction sets. This represents the union of the I, M, A,
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F, and D instruction sets listed above.
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"""
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from __future__ import absolute_import
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from . import defs
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from . import encodings, settings, registers # noqa
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# Re-export the primary target ISA definition.
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ISA = defs.ISA.finish()
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