232fb36d8f
Cretonne's encoding recipes need to have a fixed size so we can compute accurate branch destination addresses. Intel's instruction encoding has a lot of variance in the number of bytes needed to encode the opcode which leads to a number of duplicated encoding recipes that only differ in the opcode size. Add an Intel-specific TailEnc Python class which represents an abstraction over a set of recipes that are identical except for the opcode encoding. The TailEnc can then generate specific encoding recipes for each opcode format. The opcode format is a prefix of the recipe name, so for example, the 'rr' TailEnc will generate the 'Op1rr', 'Op2rr', 'Mp2rr' etc recipes. The TailEnc class provides a __call__ implementation that simply takes the sequence of opcode bytes as arguments. It then looks up the right prefix for the opcode bytes.
204 lines
6.4 KiB
Python
204 lines
6.4 KiB
Python
"""
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Intel Encoding recipes.
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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from cdsl.predicates import IsSignedInt, IsEqual
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from base.formats import Binary, BinaryImm, Store, Load
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from .registers import GPR, ABCD
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try:
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from typing import Tuple, Dict # noqa
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from cdsl.instructions import InstructionFormat # noqa
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from cdsl.isa import ConstraintSeq, BranchRange, PredNode # noqa
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except ImportError:
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pass
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# Opcode representation.
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#
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# Cretonne requires each recipe to have a single encoding size in bytes, and
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# Intel opcodes are variable length, so we use separate recipes for different
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# styles of opcodes and prefixes. The opcode format is indicated by the recipe
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# name prefix:
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OPCODE_PREFIX = {
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# Prefix bytes Name mmpp
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(): ('Op1', 0b0000),
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(0x66,): ('Mp1', 0b0001),
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(0xf3,): ('Mp1', 0b0010),
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(0xf2,): ('Mp1', 0b0011),
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(0x0f,): ('Op2', 0b0100),
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(0x66, 0x0f): ('Mp2', 0b0101),
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(0xf3, 0x0f): ('Mp2', 0b0110),
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(0xf2, 0x0f): ('Mp2', 0b0111),
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(0x0f, 0x38): ('Op3', 0b1000),
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(0x66, 0x0f, 0x38): ('Mp3', 0b1001),
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(0xf3, 0x0f, 0x38): ('Mp3', 0b1010),
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(0xf2, 0x0f, 0x38): ('Mp3', 0b1011),
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(0x0f, 0x3a): ('Op3', 0b1100),
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(0x66, 0x0f, 0x3a): ('Mp3', 0b1101),
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(0xf3, 0x0f, 0x3a): ('Mp3', 0b1110),
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(0xf2, 0x0f, 0x3a): ('Mp3', 0b1111)
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}
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# VEX/XOP and EVEX prefixes are not yet supported.
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#
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# The encoding bits are:
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#
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# 0-7: The opcode byte <op>.
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# 8-9: pp, mandatory prefix:
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# 00 none (Op*)
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# 01 66 (Mp*)
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# 10 F3 (Mp*)
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# 11 F2 (Mp*)
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# 10-11: mm, opcode map:
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# 00 <op> (Op1/Mp1)
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# 01 0F <op> (Op2/Mp2)
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# 10 0F 38 <op> (Op3/Mp3)
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# 11 0F 3A <op> (Op3/Mp3)
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# 12-14 rrr, opcode bits for the ModR/M byte for certain opcodes.
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# 15: REX.W bit (or VEX.W/E)
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#
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# There is some redundancy between bits 8-11 and the recipe names, but we have
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# enough bits, and the pp+mm format is ready for supporting VEX prefixes.
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def decode_ops(ops, rrr=0, w=0):
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# type: (Tuple[int, ...], int, int) -> Tuple[str, int]
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"""
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Given a sequence of opcode bytes, compute the recipe name prefix and
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encoding bits.
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"""
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assert rrr <= 0b111
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assert w <= 1
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name, mmpp = OPCODE_PREFIX[ops[:-1]]
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op = ops[-1]
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assert op <= 256
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return (name, op | (mmpp << 8) | (rrr << 12) | (w << 15))
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class TailRecipe:
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"""
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Generate encoding recipes on demand.
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Intel encodings are somewhat orthogonal with the opcode representation on
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one side and the ModR/M, SIB and immediate fields on the other side.
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A `TailRecipe` represents the part of an encoding that follow the opcode.
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It is used to generate full encoding recipes on demand when combined with
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an opcode.
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The arguments are the same as for an `EncRecipe`, except for `size` which
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does not include the size of the opcode.
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"""
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def __init__(
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self,
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name, # type: str
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format, # type: InstructionFormat
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size, # type: int
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ins, # type: ConstraintSeq
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outs, # type: ConstraintSeq
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branch_range=None, # type: BranchRange
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instp=None, # type: PredNode
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isap=None # type: PredNode
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):
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# type: (...) -> None
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self.name = name
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self.format = format
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self.size = size
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self.ins = ins
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self.outs = outs
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self.branch_range = branch_range
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self.instp = instp
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self.isap = isap
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# Cached recipes, keyed by name prefix.
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self.recipes = dict() # type: Dict[str, EncRecipe]
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def __call__(self, *ops, **kwargs):
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# type: (*int, **int) -> Tuple[EncRecipe, int]
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"""
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Create an encoding recipe and encoding bits for the opcode bytes in
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`ops`.
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"""
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rrr = kwargs.get('rrr', 0)
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w = kwargs.get('w', 0)
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name, bits = decode_ops(ops, rrr, w)
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if name not in self.recipes:
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self.recipes[name] = EncRecipe(
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name + self.name,
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self.format,
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len(ops) + self.size,
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ins=self.ins,
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outs=self.outs,
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branch_range=self.branch_range,
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instp=self.instp,
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isap=self.isap)
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return (self.recipes[name], bits)
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# XX /r
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rr = TailRecipe('rr', Binary, size=1, ins=(GPR, GPR), outs=0)
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# XX /n with one arg in %rcx, for shifts.
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rc = TailRecipe('rc', Binary, size=1, ins=(GPR, GPR.rcx), outs=0)
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# XX /n ib with 8-bit immediate sign-extended.
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rib = TailRecipe(
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'rib', BinaryImm, size=2, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 8))
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# XX /n id with 32-bit immediate sign-extended.
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rid = TailRecipe(
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'rid', BinaryImm, size=5, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 32))
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#
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# Store recipes.
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#
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# XX /r register-indirect store with no offset.
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st = TailRecipe(
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'st', Store, size=1, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with no offset.
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# Only ABCD allowed for stored value. This is for byte stores.
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st_abcd = TailRecipe(
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'st_abcd', Store, size=1, ins=(ABCD, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with 8-bit offset.
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stDisp8 = TailRecipe(
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'stDisp8', Store, size=2, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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stDisp8_abcd = TailRecipe(
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'stDisp8_abcd', Store, size=2, ins=(ABCD, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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# XX /r register-indirect store with 32-bit offset.
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stDisp32 = TailRecipe('stDisp32', Store, size=5, ins=(GPR, GPR), outs=())
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stDisp32_abcd = TailRecipe(
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'stDisp32_abcd', Store, size=5, ins=(ABCD, GPR), outs=())
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#
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# Load recipes
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#
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# XX /r load with no offset.
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ld = TailRecipe(
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'ld', Load, size=1, ins=(GPR), outs=(GPR),
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instp=IsEqual(Load.offset, 0))
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# XX /r load with 8-bit offset.
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ldDisp8 = TailRecipe(
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'ldDisp8', Load, size=2, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 8))
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# XX /r load with 32-bit offset.
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ldDisp32 = TailRecipe(
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'ldDisp32', Load, size=5, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 32))
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