232fb36d8f
Cretonne's encoding recipes need to have a fixed size so we can compute accurate branch destination addresses. Intel's instruction encoding has a lot of variance in the number of bytes needed to encode the opcode which leads to a number of duplicated encoding recipes that only differ in the opcode size. Add an Intel-specific TailEnc Python class which represents an abstraction over a set of recipes that are identical except for the opcode encoding. The TailEnc can then generate specific encoding recipes for each opcode format. The opcode format is a prefix of the recipe name, so for example, the 'rr' TailEnc will generate the 'Op1rr', 'Op2rr', 'Mp2rr' etc recipes. The TailEnc class provides a __call__ implementation that simply takes the sequence of opcode bytes as arguments. It then looks up the right prefix for the opcode bytes.
64 lines
2.1 KiB
Python
64 lines
2.1 KiB
Python
"""
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Intel Encodings.
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"""
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from __future__ import absolute_import
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from base import instructions as base
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from .defs import I32
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from . import recipes as r
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I32.enc(base.iadd.i32, *r.rr(0x01))
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I32.enc(base.isub.i32, *r.rr(0x29))
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I32.enc(base.band.i32, *r.rr(0x21))
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I32.enc(base.bor.i32, *r.rr(0x09))
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I32.enc(base.bxor.i32, *r.rr(0x31))
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, rrr in [
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(base.iadd_imm.i32, 0),
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(base.band_imm.i32, 4),
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(base.bor_imm.i32, 1),
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(base.bxor_imm.i32, 6)]:
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I32.enc(inst, *r.rib(0x83, rrr=rrr))
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I32.enc(inst, *r.rid(0x81, rrr=rrr))
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# 32-bit shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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I32.enc(base.ishl.i32.i32, *r.rc(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, *r.rc(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, *r.rc(0xd3, rrr=7))
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# Loads and stores.
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I32.enc(base.store.i32.i32, *r.st(0x89))
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I32.enc(base.store.i32.i32, *r.stDisp8(0x89))
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I32.enc(base.store.i32.i32, *r.stDisp32(0x89))
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I32.enc(base.istore16.i32.i32, *r.st(0x66, 0x89))
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I32.enc(base.istore16.i32.i32, *r.stDisp8(0x66, 0x89))
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I32.enc(base.istore16.i32.i32, *r.stDisp32(0x66, 0x89))
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I32.enc(base.istore8.i32.i32, *r.st_abcd(0x88))
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I32.enc(base.istore8.i32.i32, *r.stDisp8_abcd(0x88))
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I32.enc(base.istore8.i32.i32, *r.stDisp32_abcd(0x88))
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I32.enc(base.load.i32.i32, *r.ld(0x8b))
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I32.enc(base.load.i32.i32, *r.ldDisp8(0x8b))
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I32.enc(base.load.i32.i32, *r.ldDisp32(0x8b))
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I32.enc(base.uload16.i32.i32, *r.ld(0x0f, 0xb7))
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I32.enc(base.uload16.i32.i32, *r.ldDisp8(0x0f, 0xb7))
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I32.enc(base.uload16.i32.i32, *r.ldDisp32(0x0f, 0xb7))
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I32.enc(base.sload16.i32.i32, *r.ld(0x0f, 0xbf))
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I32.enc(base.sload16.i32.i32, *r.ldDisp8(0x0f, 0xbf))
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I32.enc(base.sload16.i32.i32, *r.ldDisp32(0x0f, 0xbf))
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I32.enc(base.uload8.i32.i32, *r.ld(0x0f, 0xb6))
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I32.enc(base.uload8.i32.i32, *r.ldDisp8(0x0f, 0xb6))
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I32.enc(base.uload8.i32.i32, *r.ldDisp32(0x0f, 0xb6))
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I32.enc(base.sload8.i32.i32, *r.ld(0x0f, 0xbe))
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I32.enc(base.sload8.i32.i32, *r.ldDisp8(0x0f, 0xbe))
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I32.enc(base.sload8.i32.i32, *r.ldDisp32(0x0f, 0xbe))
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