230e2135d6
* Cranelift: remove non-egraphs optimization pipeline and `use_egraphs` option. This PR removes the LICM, GVN, and preopt passes, and associated support pieces, from `cranelift-codegen`. Not to worry, we still have optimizations: the egraph framework subsumes all of these, and has been on by default since #5181. A few decision points: - Filetests for the legacy LICM, GVN and simple_preopt were removed too. As we built optimizations in the egraph framework we wrote new tests for the equivalent functionality, and many of the old tests were testing specific behaviors in the old implementations that may not be relevant anymore. However if folks prefer I could take a different approach here and try to port over all of the tests. - The corresponding filetest modes (commands) were deleted too. The `test alias_analysis` mode remains, but no longer invokes a separate GVN first (since there is no separate GVN that will not also do alias analysis) so the tests were tweaked slightly to work with that. The egrpah testsuite also covers alias analysis. - The `divconst_magic_numbers` module is removed since it's unused without `simple_preopt`, though this is the one remaining optimization we still need to build in the egraphs framework, pending #5908. The magic numbers will live forever in git history so removing this in the meantime is not a major issue IMHO. - The `use_egraphs` setting itself was removed at both the Cranelift and Wasmtime levels. It has been marked deprecated for a few releases now (Wasmtime 6.0, 7.0, upcoming 8.0, and corresponding Cranelift versions) so I think this is probably OK. As an alternative if anyone feels strongly, we could leave the setting and make it a no-op. * Update test outputs for remaining test differences.
157 lines
2.5 KiB
Plaintext
157 lines
2.5 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64
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function %f(i8, i64, i64) -> i64 {
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block0(v0: i8, v1: i64, v2: i64):
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v3 = iconst.i8 42
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v4 = icmp eq v0, v3
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v5 = select.i64 v4, v1, v2
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return v5
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}
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; VCode:
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; block0:
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; li a4,42
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; andi a3,a0,255
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; andi a4,a4,255
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; select_reg a0,a1,a2##condition=(a3 eq a4)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; addi a4, zero, 0x2a
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; andi a3, a0, 0xff
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; andi a4, a4, 0xff
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; beq a3, a4, 0xc
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; ori a0, a2, 0
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; j 8
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; ori a0, a1, 0
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; ret
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function %g(i8) -> i8 {
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block0(v0: i8):
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v3 = iconst.i8 42
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v4 = icmp eq v0, v3
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return v4
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}
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; VCode:
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; block0:
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; li a2,42
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; andi a0,a0,255
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; andi a2,a2,255
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; eq a0,a0,a2##ty=i8
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; addi a2, zero, 0x2a
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; andi a0, a0, 0xff
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; andi a2, a2, 0xff
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; bne a0, a2, 0xc
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; addi a0, zero, 1
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; j 8
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; mv a0, zero
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; ret
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function %h(i8, i8, i8) -> i8 {
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block0(v0: i8, v1: i8, v2: i8):
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v3 = bitselect.i8 v0, v1, v2
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return v3
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}
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; VCode:
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; block0:
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; and a1,a0,a1
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; not a3,a0
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; and a5,a3,a2
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; or a0,a1,a5
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; and a1, a0, a1
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; not a3, a0
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; and a5, a3, a2
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; or a0, a1, a5
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; ret
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function %i(i8, i8, i8) -> i8 {
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block0(v0: i8, v1: i8, v2: i8):
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v3 = select.i8 v0, v1, v2
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return v3
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}
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; VCode:
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; block0:
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; andi a3,a0,255
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; select_i8 a0,a1,a2##condition=a3
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; andi a3, a0, 0xff
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; beqz a3, 0xc
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; ori a0, a1, 0
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; j 8
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; ori a0, a2, 0
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; ret
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function %i(i32, i8, i8) -> i8 {
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block0(v0: i32, v1: i8, v2: i8):
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v3 = iconst.i32 42
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v4 = icmp.i32 eq v0, v3
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v5 = select.i8 v4, v1, v2
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return v5
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}
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; VCode:
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; block0:
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; li a6,42
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; slli a3,a0,32
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; srli a4,a3,32
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; slli a6,a6,32
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; srli t3,a6,32
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; select_reg a0,a1,a2##condition=(a4 eq t3)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; addi a6, zero, 0x2a
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; slli a3, a0, 0x20
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; srli a4, a3, 0x20
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; slli a6, a6, 0x20
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; srli t3, a6, 0x20
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; beq a4, t3, 0xc
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; ori a0, a2, 0
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; j 8
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; ori a0, a1, 0
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; ret
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function %i128_select(i8, i128, i128) -> i128 {
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block0(v0: i8, v1: i128, v2: i128):
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v3 = select.i128 v0, v1, v2
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return v3
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}
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; VCode:
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; block0:
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; mv a7,a1
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; andi a5,a0,255
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; select_i128 [a0,a1],[a7,a2],[a3,a4]##condition=a5
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; ori a7, a1, 0
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; andi a5, a0, 0xff
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; beqz a5, 0x10
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; ori a0, a7, 0
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; ori a1, a2, 0
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; j 0xc
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; ori a0, a3, 0
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; ori a1, a4, 0
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; ret
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