230e2135d6
* Cranelift: remove non-egraphs optimization pipeline and `use_egraphs` option. This PR removes the LICM, GVN, and preopt passes, and associated support pieces, from `cranelift-codegen`. Not to worry, we still have optimizations: the egraph framework subsumes all of these, and has been on by default since #5181. A few decision points: - Filetests for the legacy LICM, GVN and simple_preopt were removed too. As we built optimizations in the egraph framework we wrote new tests for the equivalent functionality, and many of the old tests were testing specific behaviors in the old implementations that may not be relevant anymore. However if folks prefer I could take a different approach here and try to port over all of the tests. - The corresponding filetest modes (commands) were deleted too. The `test alias_analysis` mode remains, but no longer invokes a separate GVN first (since there is no separate GVN that will not also do alias analysis) so the tests were tweaked slightly to work with that. The egrpah testsuite also covers alias analysis. - The `divconst_magic_numbers` module is removed since it's unused without `simple_preopt`, though this is the one remaining optimization we still need to build in the egraphs framework, pending #5908. The magic numbers will live forever in git history so removing this in the meantime is not a major issue IMHO. - The `use_egraphs` setting itself was removed at both the Cranelift and Wasmtime levels. It has been marked deprecated for a few releases now (Wasmtime 6.0, 7.0, upcoming 8.0, and corresponding Cranelift versions) so I think this is probably OK. As an alternative if anyone feels strongly, we could leave the setting and make it a no-op. * Update test outputs for remaining test differences.
74 lines
1.4 KiB
Plaintext
74 lines
1.4 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64 has_zbb
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;; This is a regression test for a bug in the RISC-V backend where
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;; When enabling `Zbb` the backend would try to use one of the
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;; integer instructions (`orn`) to implement a float operation
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;; causing a regalloc panic.
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function %or_not_optimization_float() -> i32 system_v {
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block0:
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v0 = iconst.i32 0
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v1 = f32const 0.0
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v2 = bnot v1
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v3 = bor v2, v2
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br_table v0, block1(v3), [block1(v1)]
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block1(v4: f32):
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return v0
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}
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; VCode:
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; block0:
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; li a0,0
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; li t1,0
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; fmv.w.x fa6,t1
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; fmv.x.w t4,fa6
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; not t1,t4
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; fmv.w.x ft8,t1
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; fmv.x.w t3,ft8
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; fmv.x.w t0,ft8
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; or t2,t3,t0
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; fmv.w.x fa1,t2
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; br_table a0,[MachLabel(1),MachLabel(2)]##tmp1=t0,tmp2=t1
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; block1:
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; j label3
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; block2:
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; fmv.d fa1,fa6
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; j label3
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; block3:
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; mv a0, zero
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; mv t1, zero
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; fmv.w.x fa6, t1
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; fmv.x.w t4, fa6
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; not t1, t4
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; fmv.w.x ft8, t1
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; fmv.x.w t3, ft8
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; fmv.x.w t0, ft8
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; or t2, t3, t0
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; fmv.w.x fa1, t2
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; slli t6, a0, 0x20
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; srli t6, t6, 0x20
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; addi t1, zero, 1
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; bltu t6, t1, 0xc
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; auipc t1, 0
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; jalr zero, t1, 0x28
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; auipc t0, 0
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; slli t1, t6, 3
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; add t0, t0, t1
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; jalr zero, t0, 0x10
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; auipc t1, 0
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; jalr zero, t1, 0xc
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; block1: ; offset 0x58
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; j 8
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; block2: ; offset 0x5c
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; fmv.d fa1, fa6
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; block3: ; offset 0x60
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; ret
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