3a2b32bf4d
* Port branches to ISLE (AArch64) Ported the existing implementations of the following opcodes for AArch64 to ISLE: - `Brz` - `Brnz` - `Brif` - `Brff` - `BrIcmp` - `Jump` - `BrTable` Copyright (c) 2022 Arm Limited * Remove dead code Copyright (c) 2022 Arm Limited
86 lines
2.4 KiB
Rust
86 lines
2.4 KiB
Rust
//! A place to park MachInst::Inst fragments which are common across multiple architectures.
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use super::{Lower, VCodeInst};
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use crate::ir::{self, Inst as IRInst};
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use smallvec::SmallVec;
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//============================================================================
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// Instruction input "slots".
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//
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// We use these types to refer to operand numbers, and result numbers, together
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// with the associated instruction, in a type-safe way.
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/// Identifier for a particular input of an instruction.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub(crate) struct InsnInput {
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pub(crate) insn: IRInst,
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pub(crate) input: usize,
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}
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/// Identifier for a particular output of an instruction.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub(crate) struct InsnOutput {
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pub(crate) insn: IRInst,
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pub(crate) output: usize,
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}
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pub(crate) fn insn_outputs<I: VCodeInst>(
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ctx: &Lower<I>,
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insn: IRInst,
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) -> SmallVec<[InsnOutput; 4]> {
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(0..ctx.num_outputs(insn))
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.map(|i| InsnOutput { insn, output: i })
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.collect()
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}
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//============================================================================
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// Atomic instructions.
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/// Atomic memory update operations.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum MachAtomicRmwOp {
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/// Add
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Add,
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/// Sub
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Sub,
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/// And
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And,
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/// Nand
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Nand,
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/// Or
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Or,
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/// Exclusive Or
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Xor,
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/// Exchange (swap operands)
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Xchg,
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/// Unsigned min
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Umin,
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/// Unsigned max
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Umax,
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/// Signed min
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Smin,
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/// Signed max
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Smax,
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}
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impl MachAtomicRmwOp {
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/// Converts an `ir::AtomicRmwOp` to the corresponding
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/// `inst_common::AtomicRmwOp`.
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pub fn from(ir_op: ir::AtomicRmwOp) -> Self {
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match ir_op {
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ir::AtomicRmwOp::Add => MachAtomicRmwOp::Add,
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ir::AtomicRmwOp::Sub => MachAtomicRmwOp::Sub,
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ir::AtomicRmwOp::And => MachAtomicRmwOp::And,
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ir::AtomicRmwOp::Nand => MachAtomicRmwOp::Nand,
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ir::AtomicRmwOp::Or => MachAtomicRmwOp::Or,
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ir::AtomicRmwOp::Xor => MachAtomicRmwOp::Xor,
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ir::AtomicRmwOp::Xchg => MachAtomicRmwOp::Xchg,
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ir::AtomicRmwOp::Umin => MachAtomicRmwOp::Umin,
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ir::AtomicRmwOp::Umax => MachAtomicRmwOp::Umax,
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ir::AtomicRmwOp::Smin => MachAtomicRmwOp::Smin,
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ir::AtomicRmwOp::Smax => MachAtomicRmwOp::Smax,
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}
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}
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}
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