1c014d129a
Addresses #3809: when we are asked to create a Cranelift backend with shared flags that indicate support for SIMD, we should check that the ISA level needed for our SIMD lowerings is present.
54 lines
1.7 KiB
Plaintext
54 lines
1.7 KiB
Plaintext
test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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function %vhighbits_i8x16(i8x16) -> i16 {
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block0(v0: i8x16):
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v1 = vhigh_bits.i16 v0
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return v1
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}
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; run: %vhighbits_i8x16([0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]) == 0
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; run: %vhighbits_i8x16([0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0]) == 0
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; run: %vhighbits_i8x16([1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7]) == 0
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; run: %vhighbits_i8x16([128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128]) == -1
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; run: %vhighbits_i8x16([128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 8]) == 32767
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function %vhighbits_i16x8(i16x8) -> i8 {
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block0(v0: i16x8):
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v1 = vhigh_bits.i8 v0
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return v1
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}
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; run: %vhighbits_i16x8([0 0 0 0 0 0 0 0]) == 0
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; run: %vhighbits_i16x8([0 0 0 0 0 0 0 1]) == 0
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; run: %vhighbits_i16x8([1 2 3 4 5 6 7 8]) == 0
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; run: %vhighbits_i16x8([128 128 128 128 128 128 128 128]) == 0
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; run: %vhighbits_i16x8([32768 32768 32768 32768 32768 32768 32768 0]) == 127
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function %vhighbits_i32x4(i32x4) -> i8 {
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block0(v0: i32x4):
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v1 = vhigh_bits.i8 v0
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return v1
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}
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; run: %vhighbits_i32x4([0 0 0 0]) == 0
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; run: %vhighbits_i32x4([0 0 0 1]) == 0
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; run: %vhighbits_i32x4([1 2 3 4]) == 0
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; run: %vhighbits_i32x4([128 128 128 128]) == 0
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; run: %vhighbits_i32x4([2147483648 2147483648 2147483648 2147483648]) == 15
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; run: %vhighbits_i32x4([2147483648 0 2147483648 0]) == 5
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function %vhighbits_i64x2(i64x2) -> i8 {
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block0(v0: i64x2):
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v1 = vhigh_bits.i8 v0
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return v1
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}
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; run: %vhighbits_i64x2([0 0]) == 0
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; run: %vhighbits_i64x2([0 1]) == 0
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; run: %vhighbits_i64x2([1 2]) == 0
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; run: %vhighbits_i64x2([128 128]) == 0
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; run: %vhighbits_i64x2([18446744073709551615 18446744073709551615]) == 3
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; run: %vhighbits_i64x2([18446744073709551615 0]) == 1
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