638dc4e0b3
This adds full support for all Cranelift SIMD instructions to the s390x target. Everything is matched fully via ISLE. In addition to adding support for many new instructions, and the lower.isle code to match all SIMD IR patterns, this patch also adds ABI support for vector types. In particular, we now need to handle the fact that vector registers 8 .. 15 are partially callee-saved, i.e. the high parts of those registers (which correspond to the old floating-poing registers) are callee-saved, but the low parts are not. This is the exact same situation that we already have on AArch64, and so this patch uses the same solution (the is_included_in_clobbers callback). The bulk of the changes are platform-specific, but there are a few exceptions: - Added ISLE extractors for the Immediate and Constant types, to enable matching the vconst and swizzle instructions. - Added a missing accessor for call_conv to ABISig. - Fixed endian conversion for vector types in data_value.rs to enable their use in runtests on the big-endian platforms. - Enabled (nearly) all SIMD runtests on s390x. [ Two test cases remain disabled due to vector shift count semantics, see below. ] - Enabled all Wasmtime SIMD tests on s390x. There are three minor issues, called out via FIXMEs below, which should be addressed in the future, but should not be blockers to getting this patch merged. I've opened the following issues to track them: - Vector shift count semantics https://github.com/bytecodealliance/wasmtime/issues/4424 - is_included_in_clobbers vs. link register https://github.com/bytecodealliance/wasmtime/issues/4425 - gen_constant callback https://github.com/bytecodealliance/wasmtime/issues/4426 All tests, including all newly enabled SIMD tests, pass on both z14 and z15 architectures.
257 lines
6.8 KiB
Plaintext
257 lines
6.8 KiB
Plaintext
test run
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target aarch64
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target s390x
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; raw_bitcast is needed to get around issue with "bint" on aarch64
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function %simd_icmp_eq_i8(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i8 0
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v3 = splat.i8x16 v1
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v2 = icmp eq v0, v3
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v4 = raw_bitcast.i8x16 v2
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return v4
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}
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; run: %simd_icmp_eq_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0 0xff 0 0 0 0xff 0 0 0 0xff 0 0 0 0xff 0 0]
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function %simd_icmp_ne_i16(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = iconst.i16 0
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v3 = splat.i16x8 v1
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v2 = icmp ne v0, v3
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v4 = raw_bitcast.i16x8 v2
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return v4
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}
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; run: %simd_icmp_ne_i16([-1 0 1 100 -1 0 1 100]) == [0xffff 0 0xffff 0xffff 0xffff 0 0xffff 0xffff]
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function %simd_icmp_le_i32(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iconst.i32 0
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v3 = splat.i32x4 v1
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v2 = icmp sle v0, v3
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_icmp_le_i32([-1 0 1 100]) == [0xffffffff 0xffffffff 0 0]
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function %simd_icmp_ge_i64(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v1 = iconst.i64 0
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v3 = splat.i64x2 v1
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v2 = icmp sge v0, v3
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_icmp_ge_i64([-1 0]) == [0 0xffffffffffffffff]
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; run: %simd_icmp_ge_i64([1 100]) == [0xffffffffffffffff 0xffffffffffffffff]
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function %simd_icmp_lt_i8(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i8 0
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v3 = splat.i8x16 v1
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v2 = icmp slt v0, v3
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v4 = raw_bitcast.i8x16 v2
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return v4
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}
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; run: %simd_icmp_lt_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0xff 0 0 0 0xff 0 0 0 0xff 0 0 0 0xff 0 0 0]
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function %simd_icmp_gt_i16(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = iconst.i16 0
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v3 = splat.i16x8 v1
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v2 = icmp sgt v0, v3
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v4 = raw_bitcast.i16x8 v2
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return v4
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}
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; run: %simd_icmp_gt_i16([-1 0 1 100 -1 0 1 100]) == [0 0 0xffff 0xffff 0 0 0xffff 0xffff]
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function %simd_fcmp_eq_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp eq v0, v3
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_eq_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0 0xffffffff 0 0]
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function %simd_fcmp_ne_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp ne v0, v3
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_ne_f64([-0x1.0 0x0.0]) == [0xffffffffffffffff 0]
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; run: %simd_fcmp_ne_f64([0x1.0 NaN]) == [0xffffffffffffffff 0xffffffffffffffff]
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function %simd_fcmp_le_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp le v0, v3
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_le_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0xffffffff 0 0]
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function %simd_fcmp_ge_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp ge v0, v3
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_ge_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
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; run: %simd_fcmp_ge_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
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function %simd_fcmp_lt_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp lt v0, v3
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_lt_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0 0]
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function %simd_fcmp_gt_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp gt v0, v3
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_gt_f64([-0x1.0 0x0.0]) == [0 0]
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; run: %simd_fcmp_gt_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
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function %simd_icmp_eq_i32(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iconst.i32 0
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v3 = splat.i32x4 v1
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v2 = icmp eq v3, v0
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_icmp_eq_i32([1 0 -1 100]) == [0 0xffffffff 0 0]
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function %simd_icmp_ne_i64(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v1 = iconst.i64 0
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v3 = splat.i64x2 v1
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v2 = icmp ne v3, v0
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_icmp_ne_i64([-1 0]) == [0xffffffffffffffff 0]
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; run: %simd_icmp_ne_i64([1 100]) == [0xffffffffffffffff 0xffffffffffffffff]
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function %simd_icmp_le_i8(i8x16) -> i8x16 {
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block0(v0: i8x16):
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v1 = iconst.i8 0
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v3 = splat.i8x16 v1
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v2 = icmp sle v3, v0
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v4 = raw_bitcast.i8x16 v2
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return v4
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}
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; run: %simd_icmp_le_i8([-1 0 1 100 -1 0 1 100 -1 0 1 100 -1 0 1 100]) == [0 0xff 0xff 0xff 0 0xff 0xff 0xff 0 0xff 0xff 0xff 0 0xff 0xff 0xff]
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function %simd_icmp_ge_i16(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = iconst.i16 0
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v3 = splat.i16x8 v1
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v2 = icmp sge v3, v0
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v4 = raw_bitcast.i16x8 v2
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return v4
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}
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; run: %simd_icmp_ge_i16([-1 0 1 100 -1 0 1 100]) == [0xffff 0xffff 0 0 0xffff 0xffff 0 0]
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function %simd_icmp_lt_i32(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iconst.i32 0
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v3 = splat.i32x4 v1
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v2 = icmp slt v3, v0
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_icmp_lt_i32([-1 0 1 100]) == [0 0 0xffffffff 0xffffffff]
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function %simd_icmp_gt_i64(i64x2) -> i64x2 {
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block0(v0: i64x2):
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v1 = iconst.i64 0
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v3 = splat.i64x2 v1
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v2 = icmp sgt v3, v0
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_icmp_gt_i64([-1 0]) == [0xffffffffffffffff 0]
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; run: %simd_icmp_gt_i64([1 100]) == [0 0]
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function %simd_fcmp_eq_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp eq v3, v0
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_eq_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
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; run: %simd_fcmp_eq_f64([0x1.0 NaN]) == [0 0]
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function %simd_fcmp_ne_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp ne v3, v0
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_ne_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0xffffffff 0xffffffff]
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function %simd_fcmp_le_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp le v3, v0
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_le_f64([-0x1.0 0x0.0]) == [0 0xffffffffffffffff]
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; run: %simd_fcmp_le_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
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function %simd_fcmp_ge_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp ge v3, v0
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_ge_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0xffffffff 0 0]
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function %simd_fcmp_lt_f64(f64x2) -> i64x2 {
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block0(v0: f64x2):
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v1 = f64const 0.0
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v3 = splat.f64x2 v1
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v2 = fcmp lt v3, v0
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v4 = raw_bitcast.i64x2 v2
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return v4
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}
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; run: %simd_fcmp_lt_f64([-0x1.0 0x0.0]) == [0 0]
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; run: %simd_fcmp_lt_f64([0x1.0 NaN]) == [0xffffffffffffffff 0]
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function %simd_fcmp_gt_f32(f32x4) -> i32x4 {
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block0(v0: f32x4):
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v1 = f32const 0.0
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v3 = splat.f32x4 v1
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v2 = fcmp gt v3, v0
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v4 = raw_bitcast.i32x4 v2
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return v4
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}
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; run: %simd_fcmp_gt_f32([-0x1.0 0x0.0 0x1.0 NaN]) == [0xffffffff 0 0 0]
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