1ef0abb12c
* Update lots of `isa/*/*.clif` tests to `precise-output` This commit goes through the `aarch64` and `x64` subdirectories and subjectively changes tests from `test compile` to add `precise-output`. This then auto-updates all the test expectations so they can be automatically instead of manually updated in the future. Not all tests were migrated, largely subject to the whims of myself, mainly looking to see if the test was looking for specific instructions or just checking the whole assembly output. * Filter out `;;` comments from test expctations Looks like the cranelift parser picks up all comments, not just those trailing the function, so use a convention where `;;` is used for human-readable-comments in test cases and `;`-prefixed comments are the test expectation.
395 lines
9.1 KiB
Plaintext
395 lines
9.1 KiB
Plaintext
test compile precise-output
|
|
set enable_simd
|
|
target x86_64 skylake
|
|
|
|
function %band_f32x4(f32x4, f32x4) -> f32x4 {
|
|
block0(v0: f32x4, v1: f32x4):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: andps %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %band_f64x2(f64x2, f64x2) -> f64x2 {
|
|
block0(v0: f64x2, v1: f64x2):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: andpd %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %band_i32x4(i32x4, i32x4) -> i32x4 {
|
|
block0(v0: i32x4, v1: i32x4):
|
|
v2 = band v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: pand %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bor_f32x4(f32x4, f32x4) -> f32x4 {
|
|
block0(v0: f32x4, v1: f32x4):
|
|
v2 = bor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: orps %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bor_f64x2(f64x2, f64x2) -> f64x2 {
|
|
block0(v0: f64x2, v1: f64x2):
|
|
v2 = bor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: orpd %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bor_i32x4(i32x4, i32x4) -> i32x4 {
|
|
block0(v0: i32x4, v1: i32x4):
|
|
v2 = bor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: por %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bxor_f32x4(f32x4, f32x4) -> f32x4 {
|
|
block0(v0: f32x4, v1: f32x4):
|
|
v2 = bxor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: xorps %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bxor_f64x2(f64x2, f64x2) -> f64x2 {
|
|
block0(v0: f64x2, v1: f64x2):
|
|
v2 = bxor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: xorpd %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bxor_i32x4(i32x4, i32x4) -> i32x4 {
|
|
block0(v0: i32x4, v1: i32x4):
|
|
v2 = bxor v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 6)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: pxor %xmm1, %xmm0
|
|
; Inst 3: movq %rbp, %rsp
|
|
; Inst 4: popq %rbp
|
|
; Inst 5: ret
|
|
; }}
|
|
|
|
function %bitselect_i16x8() -> i16x8 {
|
|
block0:
|
|
v0 = vconst.i16x8 [0 0 0 0 0 0 0 0]
|
|
v1 = vconst.i16x8 [0 0 0 0 0 0 0 0]
|
|
v2 = vconst.i16x8 [0 0 0 0 0 0 0 0]
|
|
v3 = bitselect v0, v1, v2
|
|
return v3
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 11)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: load_const VCodeConstant(0), %xmm0
|
|
; Inst 3: load_const VCodeConstant(0), %xmm1
|
|
; Inst 4: load_const VCodeConstant(0), %xmm2
|
|
; Inst 5: pand %xmm0, %xmm1
|
|
; Inst 6: pandn %xmm2, %xmm0
|
|
; Inst 7: por %xmm1, %xmm0
|
|
; Inst 8: movq %rbp, %rsp
|
|
; Inst 9: popq %rbp
|
|
; Inst 10: ret
|
|
; }}
|
|
|
|
function %vselect_i16x8(b16x8, i16x8, i16x8) -> i16x8 {
|
|
block0(v0: b16x8, v1: i16x8, v2: i16x8):
|
|
v3 = vselect v0, v1, v2
|
|
return v3
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 7)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: pblendvb %xmm1, %xmm2
|
|
; Inst 3: movdqa %xmm2, %xmm0
|
|
; Inst 4: movq %rbp, %rsp
|
|
; Inst 5: popq %rbp
|
|
; Inst 6: ret
|
|
; }}
|
|
|
|
function %vselect_f32x4(b32x4, f32x4, f32x4) -> f32x4 {
|
|
block0(v0: b32x4, v1: f32x4, v2: f32x4):
|
|
v3 = vselect v0, v1, v2
|
|
return v3
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 7)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: blendvps %xmm1, %xmm2
|
|
; Inst 3: movdqa %xmm2, %xmm0
|
|
; Inst 4: movq %rbp, %rsp
|
|
; Inst 5: popq %rbp
|
|
; Inst 6: ret
|
|
; }}
|
|
|
|
function %vselect_f64x2(b64x2, f64x2, f64x2) -> f64x2 {
|
|
block0(v0: b64x2, v1: f64x2, v2: f64x2):
|
|
v3 = vselect v0, v1, v2
|
|
return v3
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 7)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: blendvpd %xmm1, %xmm2
|
|
; Inst 3: movdqa %xmm2, %xmm0
|
|
; Inst 4: movq %rbp, %rsp
|
|
; Inst 5: popq %rbp
|
|
; Inst 6: ret
|
|
; }}
|
|
|
|
function %ishl_i8x16(i32) -> i8x16 {
|
|
block0(v0: i32):
|
|
v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
|
|
v2 = ishl v1, v0
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 12)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: load_const VCodeConstant(1), %xmm0
|
|
; Inst 3: movd %edi, %xmm1
|
|
; Inst 4: psllw %xmm1, %xmm0
|
|
; Inst 5: lea const(VCodeConstant(0)), %rsi
|
|
; Inst 6: shlq $4, %rdi
|
|
; Inst 7: movdqu 0(%rsi,%rdi,1), %xmm1
|
|
; Inst 8: pand %xmm1, %xmm0
|
|
; Inst 9: movq %rbp, %rsp
|
|
; Inst 10: popq %rbp
|
|
; Inst 11: ret
|
|
; }}
|
|
|
|
function %ushr_i8x16_imm() -> i8x16 {
|
|
block0:
|
|
v0 = iconst.i32 1
|
|
v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
|
|
v2 = ushr v1, v0
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 9)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: load_const VCodeConstant(1), %xmm0
|
|
; Inst 3: psrlw $1, %xmm0
|
|
; Inst 4: movdqu const(VCodeConstant(0)), %xmm1
|
|
; Inst 5: pand %xmm1, %xmm0
|
|
; Inst 6: movq %rbp, %rsp
|
|
; Inst 7: popq %rbp
|
|
; Inst 8: ret
|
|
; }}
|
|
|
|
function %sshr_i8x16(i32) -> i8x16 {
|
|
block0(v0: i32):
|
|
v1 = vconst.i8x16 [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15]
|
|
v2 = sshr v1, v0
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 15)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: load_const VCodeConstant(0), %xmm0
|
|
; Inst 3: addl $8, %edi
|
|
; Inst 4: movd %edi, %xmm2
|
|
; Inst 5: movdqa %xmm0, %xmm1
|
|
; Inst 6: punpcklbw %xmm1, %xmm1
|
|
; Inst 7: psraw %xmm2, %xmm1
|
|
; Inst 8: punpckhbw %xmm0, %xmm0
|
|
; Inst 9: psraw %xmm2, %xmm0
|
|
; Inst 10: packsswb %xmm0, %xmm1
|
|
; Inst 11: movdqa %xmm1, %xmm0
|
|
; Inst 12: movq %rbp, %rsp
|
|
; Inst 13: popq %rbp
|
|
; Inst 14: ret
|
|
; }}
|
|
|
|
function %sshr_i8x16_imm(i8x16, i32) -> i8x16 {
|
|
block0(v0: i8x16, v1: i32):
|
|
v2 = sshr_imm v0, 3
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 12)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: movdqa %xmm0, %xmm1
|
|
; Inst 3: movdqa %xmm1, %xmm0
|
|
; Inst 4: punpcklbw %xmm0, %xmm0
|
|
; Inst 5: psraw $11, %xmm0
|
|
; Inst 6: punpckhbw %xmm1, %xmm1
|
|
; Inst 7: psraw $11, %xmm1
|
|
; Inst 8: packsswb %xmm1, %xmm0
|
|
; Inst 9: movq %rbp, %rsp
|
|
; Inst 10: popq %rbp
|
|
; Inst 11: ret
|
|
; }}
|
|
|
|
function %sshr_i64x2(i64x2, i32) -> i64x2 {
|
|
block0(v0: i64x2, v1: i32):
|
|
v2 = sshr v0, v1
|
|
return v2
|
|
}
|
|
|
|
; VCode_ShowWithRRU {{
|
|
; Entry block: 0
|
|
; Block 0:
|
|
; (original IR block: block0)
|
|
; (instruction range: 0 .. 15)
|
|
; Inst 0: pushq %rbp
|
|
; Inst 1: movq %rsp, %rbp
|
|
; Inst 2: movdqa %xmm0, %xmm1
|
|
; Inst 3: pextrd.w $0, %xmm0, %rsi
|
|
; Inst 4: pextrd.w $1, %xmm0, %rax
|
|
; Inst 5: movq %rdi, %rcx
|
|
; Inst 6: sarq %cl, %rsi
|
|
; Inst 7: movq %rdi, %rcx
|
|
; Inst 8: sarq %cl, %rax
|
|
; Inst 9: pinsrd.w $0, %rsi, %xmm1
|
|
; Inst 10: pinsrd.w $1, %rax, %xmm1
|
|
; Inst 11: movdqa %xmm1, %xmm0
|
|
; Inst 12: movq %rbp, %rsp
|
|
; Inst 13: popq %rbp
|
|
; Inst 14: ret
|
|
; }}
|
|
|