Files
wasmtime/cranelift/filetests/filetests/isa/s390x/vec-constants.clif
Ulrich Weigand 638dc4e0b3 s390x: Implement full SIMD support (#4427)
This adds full support for all Cranelift SIMD instructions
to the s390x target.  Everything is matched fully via ISLE.

In addition to adding support for many new instructions,
and the lower.isle code to match all SIMD IR patterns,
this patch also adds ABI support for vector types.
In particular, we now need to handle the fact that
vector registers 8 .. 15 are partially callee-saved,
i.e. the high parts of those registers (which correspond
to the old floating-poing registers) are callee-saved,
but the low parts are not.  This is the exact same situation
that we already have on AArch64, and so this patch uses the
same solution (the is_included_in_clobbers callback).

The bulk of the changes are platform-specific, but there are
a few exceptions:

- Added ISLE extractors for the Immediate and Constant types,
  to enable matching the vconst and swizzle instructions.

- Added a missing accessor for call_conv to ABISig.

- Fixed endian conversion for vector types in data_value.rs
  to enable their use in runtests on the big-endian platforms.

- Enabled (nearly) all SIMD runtests on s390x.  [ Two test cases
  remain disabled due to vector shift count semantics, see below. ]

- Enabled all Wasmtime SIMD tests on s390x.

There are three minor issues, called out via FIXMEs below,
which should be addressed in the future, but should not be
blockers to getting this patch merged.  I've opened the
following issues to track them:

- Vector shift count semantics
  https://github.com/bytecodealliance/wasmtime/issues/4424

- is_included_in_clobbers vs. link register
  https://github.com/bytecodealliance/wasmtime/issues/4425

- gen_constant callback
  https://github.com/bytecodealliance/wasmtime/issues/4426

All tests, including all newly enabled SIMD tests, pass
on both z14 and z15 architectures.
2022-07-18 14:00:48 -07:00

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test compile precise-output
target s390x
function %vconst_i64x2_zero() -> i64x2 {
block0:
v1 = vconst.i64x2 [0 0]
return v1
}
; block0:
; vgbm %v24, 0
; br %r14
function %vconst_i64x2_splat1() -> i64x2 {
block0:
v1 = vconst.i64x2 [32767 32767]
return v1
}
; block0:
; vrepig %v24, 32767
; br %r14
function %vconst_i64x2_splat2() -> i64x2 {
block0:
v1 = vconst.i64x2 [-32768 -32768]
return v1
}
; block0:
; vrepig %v24, -32768
; br %r14
function %vconst_i64x2_splat3() -> i64x2 {
block0:
v1 = vconst.i64x2 [32768 32768]
return v1
}
; block0:
; bras %r1, 12 ; data.u64 0x0000000000008000 ; vlrepg %v24, 0(%r1)
; br %r14
function %vconst_i64x2_splat4() -> i64x2 {
block0:
v1 = vconst.i64x2 [-32769 -32769]
return v1
}
; block0:
; bras %r1, 12 ; data.u64 0xffffffffffff7fff ; vlrepg %v24, 0(%r1)
; br %r14
function %vconst_i64x2_mixed() -> i64x2 {
block0:
v1 = vconst.i64x2 [1 2]
return v1
}
; block0:
; bras %r1, 20 ; data.u128 0x00000000000000020000000000000001 ; vl %v24, 0(%r1)
; br %r14
function %vconst_i32x4_zero() -> i32x4 {
block0:
v1 = vconst.i32x4 [0 0 0 0]
return v1
}
; block0:
; vgbm %v24, 0
; br %r14
function %vconst_i32x4_splat1() -> i32x4 {
block0:
v1 = vconst.i32x4 [32767 32767 32767 32767]
return v1
}
; block0:
; vrepif %v24, 32767
; br %r14
function %vconst_i32x4_splat2() -> i32x4 {
block0:
v1 = vconst.i32x4 [-32768 -32768 -32768 -32768]
return v1
}
; block0:
; vrepif %v24, -32768
; br %r14
function %vconst_i32x4_splat3() -> i32x4 {
block0:
v1 = vconst.i32x4 [32768 32768 32768 32768]
return v1
}
; block0:
; bras %r1, 8 ; data.u32 0x00008000 ; vlrepf %v24, 0(%r1)
; br %r14
function %vconst_i32x4_splat4() -> i32x4 {
block0:
v1 = vconst.i32x4 [-32769 -32769 -32769 -32769]
return v1
}
; block0:
; bras %r1, 8 ; data.u32 0xffff7fff ; vlrepf %v24, 0(%r1)
; br %r14
function %vconst_i32x4_splat_i64() -> i32x4 {
block0:
v1 = vconst.i32x4 [1 2 1 2]
return v1
}
; block0:
; bras %r1, 12 ; data.u64 0x0000000200000001 ; vlrepg %v24, 0(%r1)
; br %r14
function %vconst_i32x4_mixed() -> i32x4 {
block0:
v1 = vconst.i32x4 [1 2 3 4]
return v1
}
; block0:
; bras %r1, 20 ; data.u128 0x00000004000000030000000200000001 ; vl %v24, 0(%r1)
; br %r14
function %vconst_i16x8_zero() -> i16x8 {
block0:
v1 = vconst.i16x8 [0 0 0 0 0 0 0 0]
return v1
}
; block0:
; vgbm %v24, 0
; br %r14
function %vconst_i16x8_splat1() -> i16x8 {
block0:
v1 = vconst.i16x8 [32767 32767 32767 32767 32767 32767 32767 32767]
return v1
}
; block0:
; vrepih %v24, 32767
; br %r14
function %vconst_i16x8_splat2() -> i16x8 {
block0:
v1 = vconst.i16x8 [-32768 -32768 -32768 -32768 -32768 -32768 -32768 -32768]
return v1
}
; block0:
; vrepih %v24, -32768
; br %r14
function %vconst_i16x8_mixed() -> i16x8 {
block0:
v1 = vconst.i16x8 [1 2 3 4 5 6 7 8]
return v1
}
; block0:
; bras %r1, 20 ; data.u128 0x00080007000600050004000300020001 ; vl %v24, 0(%r1)
; br %r14
function %vconst_i8x16_zero() -> i8x16 {
block0:
v1 = vconst.i8x16 [0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
return v1
}
; block0:
; vgbm %v24, 0
; br %r14
function %vconst_i8x16_splat1() -> i8x16 {
block0:
v1 = vconst.i8x16 [127 127 127 127 127 127 127 127 127 127 127 127 127 127 127 127]
return v1
}
; block0:
; vrepib %v24, 127
; br %r14
function %vconst_i8x16_splat2() -> i8x16 {
block0:
v1 = vconst.i8x16 [-128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128 -128]
return v1
}
; block0:
; vrepib %v24, 128
; br %r14
function %vconst_i8x16_mixed() -> i8x16 {
block0:
v1 = vconst.i8x16 [1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]
return v1
}
; block0:
; bras %r1, 20 ; data.u128 0x100f0e0d0c0b0a090807060504030201 ; vl %v24, 0(%r1)
; br %r14