1e1baec50a
Try to keep our Python sources compatible with both Python 2.7 and 3. Check with 'pylint --py3k' and 'python -3'.
15 lines
314 B
Python
15 lines
314 B
Python
"""
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RISC-V definitions.
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Commonly used definitions.
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"""
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from __future__ import absolute_import
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from cretonne import TargetISA, CPUMode
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import cretonne.base
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isa = TargetISA('riscv', [cretonne.base.instructions])
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# CPU modes for 32-bit and 64-bit operation.
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RV32 = CPUMode('RV32', isa)
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RV64 = CPUMode('RV64', isa)
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