1da15a10d7
Add new instruction predicates to support the 'I' encoding recipe: IsSignedInt, IsUnsignedInt used to test that an immediate operand is in the allowed range.
45 lines
1.6 KiB
Python
45 lines
1.6 KiB
Python
"""
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RISC-V Encodings.
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"""
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from __future__ import absolute_import
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from cretonne import base
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from .defs import RV32, RV64
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from .recipes import OPIMM, OPIMM32, OP, OP32, R, Rshamt, I
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# Basic arithmetic binary instructions are encoded in an R-type instruction.
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for inst, inst_imm, f3, f7 in [
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(base.iadd, base.iadd_imm, 0b000, 0b0000000),
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(base.isub, None, 0b000, 0b0100000),
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(base.bxor, base.bxor_imm, 0b100, 0b0000000),
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(base.bor, base.bor_imm, 0b110, 0b0000000),
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(base.band, base.band_imm, 0b111, 0b0000000)
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]:
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RV32.enc(inst.i32, R, OP(f3, f7))
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RV64.enc(inst.i64, R, OP(f3, f7))
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# Immediate versions for add/xor/or/and.
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if inst_imm:
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RV32.enc(inst_imm.i32, I, OPIMM(f3))
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RV64.enc(inst_imm.i64, I, OPIMM(f3))
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# There are no andiw/oriw/xoriw variations.
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RV64.enc(base.iadd_imm.i32, I, OPIMM32(0b000))
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# Dynamic shifts have the same masking semantics as the cton base instructions.
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for inst, inst_imm, f3, f7 in [
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(base.ishl, base.ishl_imm, 0b001, 0b0000000),
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(base.ushr, base.ushr_imm, 0b101, 0b0000000),
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(base.sshr, base.sshr_imm, 0b101, 0b0100000),
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]:
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RV32.enc(inst.i32.i32, R, OP(f3, f7))
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RV64.enc(inst.i64.i64, R, OP(f3, f7))
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RV64.enc(inst.i32.i32, R, OP32(f3, f7))
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# Allow i32 shift amounts in 64-bit shifts.
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RV64.enc(inst.i64.i32, R, OP(f3, f7))
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RV64.enc(inst.i32.i64, R, OP32(f3, f7))
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# Immediate shifts.
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RV32.enc(inst_imm.i32, Rshamt, OPIMM(f3, f7))
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RV64.enc(inst_imm.i64, Rshamt, OPIMM(f3, f7))
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RV64.enc(inst_imm.i32, Rshamt, OPIMM32(f3, f7))
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