19ac05577c
The intel, arm32, and arm32 targets were only defined in the meta language previously. Add Rust implementations too. This is mostly boilerplate, except for the unit tests in the registers.rs files.
74 lines
2.1 KiB
Rust
74 lines
2.1 KiB
Rust
//! ARM 32-bit Instruction Set Architecture.
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pub mod settings;
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mod enc_tables;
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mod registers;
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use super::super::settings as shared_settings;
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use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, general_encoding};
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use isa::Builder as IsaBuilder;
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use isa::{TargetIsa, RegInfo, Encoding, Legalize};
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use ir::{InstructionData, DataFlowGraph};
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#[allow(dead_code)]
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struct Isa {
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shared_flags: shared_settings::Flags,
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isa_flags: settings::Flags,
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cpumode: &'static [shared_enc_tables::Level1Entry<u16>],
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}
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/// Get an ISA builder for creating ARM32 targets.
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pub fn isa_builder() -> IsaBuilder {
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IsaBuilder {
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setup: settings::builder(),
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constructor: isa_constructor,
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}
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}
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fn isa_constructor(shared_flags: shared_settings::Flags,
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builder: &shared_settings::Builder)
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-> Box<TargetIsa> {
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let level1 = if shared_flags.is_compressed() {
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&enc_tables::LEVEL1_T32[..]
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} else {
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&enc_tables::LEVEL1_A32[..]
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};
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Box::new(Isa {
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isa_flags: settings::Flags::new(&shared_flags, builder),
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shared_flags: shared_flags,
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cpumode: level1,
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})
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}
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impl TargetIsa for Isa {
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fn name(&self) -> &'static str {
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"arm32"
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}
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fn flags(&self) -> &shared_settings::Flags {
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&self.shared_flags
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}
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fn register_info(&self) -> &RegInfo {
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®isters::INFO
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}
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fn encode(&self, _: &DataFlowGraph, inst: &InstructionData) -> Result<Encoding, Legalize> {
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lookup_enclist(inst.first_type(),
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inst.opcode(),
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self.cpumode,
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&enc_tables::LEVEL2[..])
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.and_then(|enclist_offset| {
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general_encoding(enclist_offset,
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&enc_tables::ENCLISTS[..],
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|instp| enc_tables::check_instp(inst, instp),
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|isap| self.isa_flags.numbered_predicate(isap as usize))
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.ok_or(Legalize::Expand)
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})
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}
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fn recipe_names(&self) -> &'static [&'static str] {
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&enc_tables::RECIPE_NAMES[..]
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}
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}
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