186c7c3b89
* x64: clean up regalloc-related semantics on several instructions. This PR removes all uses of "modify" operands on instructions in the x64 backend, and also removes all uses of "pinned vregs", or vregs that are explicitly tied to particular physical registers. In place of both of these mechanisms, which are legacies of the old regalloc design and supported via compatibility code, the backend now uses operand constraints. This is more flexible as it allows the regalloc to see the liveranges and constraints without "reverse-engineering" move instructions. Eventually, after removing all such uses (including in other backends and by the ABI code), we can remove the compatibility code in regalloc2, significantly simplifying its liverange-construction frontend and thus allowing for higher confidence in correctness as well as possibly a bit more compilation speed. Curiously, there are a few extra move instructions now; they are likely poor splitting decisions and I can try to chase these down later. * Fix cranelift-codegen tests. * Review feedback.
57 lines
1.4 KiB
Plaintext
57 lines
1.4 KiB
Plaintext
test compile
|
|
set avoid_div_traps=false
|
|
target x86_64
|
|
|
|
;; We should get the checked-div/rem sequence (`srem` pseudoinst below) even
|
|
;; when `avoid_div_traps` above is false (i.e. even when the host is normally
|
|
;; willing to accept SIGFPEs as Wasm traps). The machine will SIGFPE in some
|
|
;; cases when `srem` is valid (specifically -INT_MIN % -1).
|
|
|
|
function %i8(i8, i8) -> i8 {
|
|
block0(v0: i8, v1: i8):
|
|
v2 = srem.i8 v0, v1
|
|
; check: xorl %r11d, %r11d, %r11d
|
|
; nextln: movq %rdi, %rax
|
|
; nextln: movq %r11, %rdx
|
|
; nextln: srem_seq %al, %dl, %sil, %al, %dl, tmp=(none)
|
|
; nextln: shrq $$8, %rax, %rax
|
|
|
|
return v2
|
|
}
|
|
|
|
function %i16(i16, i16) -> i16 {
|
|
block0(v0: i16, v1: i16):
|
|
v2 = srem.i16 v0, v1
|
|
; check: xorl %r11d, %r11d, %r11d
|
|
; nextln: movq %rdi, %rax
|
|
; nextln: movq %r11, %rdx
|
|
; nextln: srem_seq %ax, %dx, %si, %ax, %dx, tmp=(none)
|
|
; nextln: movq %rdx, %rax
|
|
|
|
return v2
|
|
}
|
|
|
|
function %i32(i32, i32) -> i32 {
|
|
block0(v0: i32, v1: i32):
|
|
v2 = srem.i32 v0, v1
|
|
; check: xorl %r11d, %r11d, %r11d
|
|
; nextln: movq %rdi, %rax
|
|
; nextln: movq %r11, %rdx
|
|
; nextln: srem_seq %eax, %edx, %esi, %eax, %edx, tmp=(none)
|
|
; nextln: movq %rdx, %rax
|
|
|
|
return v2
|
|
}
|
|
|
|
function %i64(i64, i64) -> i64 {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = srem.i64 v0, v1
|
|
; check: xorl %r11d, %r11d, %r11d
|
|
; nextln: movq %rdi, %rax
|
|
; nextln: movq %r11, %rdx
|
|
; nextln: srem_seq %rax, %rdx, %rsi, %rax, %rdx, tmp=(none)
|
|
; nextln: movq %rdx, %rax
|
|
|
|
return v2
|
|
}
|