17cef9140c
compilation. This saves ~0.14% instruction count, ~0.18% allocated bytes, and ~1.5% allocated blocks on a `clif-util wasm` compilation of `bz2.wasm` for aarch64.
77 lines
2.1 KiB
Rust
77 lines
2.1 KiB
Rust
//! Compilation backend pipeline: optimized IR to VCode / binemit.
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use crate::ir::Function;
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use crate::machinst::*;
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use crate::settings;
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use crate::timing;
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use log::debug;
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use regalloc::{allocate_registers_with_opts, Algorithm, Options};
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/// Compile the given function down to VCode with allocated registers, ready
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/// for binary emission.
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pub fn compile<B: LowerBackend + MachBackend>(
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f: &Function,
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b: &B,
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abi: Box<dyn ABIBody<I = B::MInst>>,
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) -> CodegenResult<VCode<B::MInst>>
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where
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B::MInst: ShowWithRRU,
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{
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// This lowers the CL IR.
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let mut vcode = Lower::new(f, abi)?.lower(b)?;
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debug!(
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"vcode from lowering: \n{}",
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vcode.show_rru(Some(b.reg_universe()))
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);
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// Perform register allocation.
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let (run_checker, algorithm) = match vcode.flags().regalloc() {
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settings::Regalloc::Backtracking => (false, Algorithm::Backtracking(Default::default())),
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settings::Regalloc::BacktrackingChecked => {
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(true, Algorithm::Backtracking(Default::default()))
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}
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settings::Regalloc::ExperimentalLinearScan => {
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(false, Algorithm::LinearScan(Default::default()))
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}
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};
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let result = {
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let _tt = timing::regalloc();
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allocate_registers_with_opts(
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&mut vcode,
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b.reg_universe(),
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Options {
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run_checker,
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algorithm,
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},
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)
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.map_err(|err| {
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debug!(
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"Register allocation error for vcode\n{}\nError: {:?}",
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vcode.show_rru(Some(b.reg_universe())),
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err
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);
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err
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})
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.expect("register allocation")
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};
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// Reorder vcode into final order and copy out final instruction sequence
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// all at once. This also inserts prologues/epilogues.
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vcode.replace_insns_from_regalloc(result);
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vcode.remove_redundant_branches();
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// Do final passes over code to finalize branches.
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vcode.finalize_branches();
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debug!(
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"vcode after regalloc: final version:\n{}",
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vcode.show_rru(Some(b.reg_universe()))
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);
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Ok(vcode)
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}
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