94bcbe8446
* Port `Fcopysign`..``FcvtToSintSat` to ISLE (AArch64)
Ported the existing implementations of the following opcodes to ISLE on
AArch64:
- `Fcopysign`
- Also introduced missing support for `fcopysign` on vector values, as
per the docs.
- This introduces the vector encoding for the `SLI` machine
instruction.
- `FcvtToUint`
- `FcvtToSint`
- `FcvtFromUint`
- `FcvtFromSint`
- `FcvtToUintSat`
- `FcvtToSintSat`
Copyright (c) 2022 Arm Limited
* Document helpers and abstract conversion checks
125 lines
1.8 KiB
Plaintext
125 lines
1.8 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function u0:0(i8) -> f32 {
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block0(v0: i8):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; block0:
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; uxtb w3, w0
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; ucvtf s0, w3
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; ret
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function u0:0(i8) -> f64 {
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block0(v0: i8):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; block0:
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; uxtb w3, w0
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; ucvtf d0, w3
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; ret
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function u0:0(i16) -> f32 {
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block0(v0: i16):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; block0:
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; uxth w3, w0
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; ucvtf s0, w3
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; ret
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function u0:0(i16) -> f64 {
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block0(v0: i16):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; block0:
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; uxth w3, w0
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; ucvtf d0, w3
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; ret
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function u0:0(f32) -> i8 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i8 v0
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return v1
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}
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; block0:
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; fcmp s0, s0
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; b.vc 8 ; udf
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; fmov s5, #-1
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; fcmp s0, s5
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; b.gt 8 ; udf
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; movz x10, #17280, LSL #16
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; fmov s18, w10
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; fcmp s0, s18
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; b.lt 8 ; udf
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; fcvtzu w0, s0
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; ret
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function u0:0(f64) -> i8 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i8 v0
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return v1
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}
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; block0:
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; fcmp d0, d0
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; b.vc 8 ; udf
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; fmov d5, #-1
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; fcmp d0, d5
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; b.gt 8 ; udf
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; movz x10, #16496, LSL #48
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; fmov d18, x10
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; fcmp d0, d18
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; b.lt 8 ; udf
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; fcvtzu w0, d0
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; ret
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function u0:0(f32) -> i16 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i16 v0
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return v1
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}
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; block0:
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; fcmp s0, s0
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; b.vc 8 ; udf
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; fmov s5, #-1
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; fcmp s0, s5
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; b.gt 8 ; udf
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; movz x10, #18304, LSL #16
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; fmov s18, w10
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; fcmp s0, s18
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; b.lt 8 ; udf
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; fcvtzu w0, s0
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; ret
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function u0:0(f64) -> i16 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i16 v0
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return v1
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}
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; block0:
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; fcmp d0, d0
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; b.vc 8 ; udf
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; fmov d5, #-1
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; fcmp d0, d5
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; b.gt 8 ; udf
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; movz x10, #16624, LSL #48
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; fmov d18, x10
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; fcmp d0, d18
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; b.lt 8 ; udf
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; fcvtzu w0, d0
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; ret
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