ae5fe8a728
This PR removes all uses of modify-operands in the aarch64 backend, replacing them with reused-input operands instead. This has the nice effect of removing a bunch of move instructions and more clearly representing inputs and outputs. This PR also removes the explicit use of pinned vregs in the aarch64 backend, instead using fixed-register constraints on the operands when insts or pseudo-inst sequences require certain registers. This is the second PR in the regalloc-semantics cleanup series; after the remaining backend (s390x) and the ABI code are cleaned up as well, we'll be able to simplify the regalloc2 frontend.
289 lines
5.2 KiB
Plaintext
289 lines
5.2 KiB
Plaintext
test compile precise-output
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target aarch64
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function %snarrow_i16x4(i16) -> i8x8 {
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gv0 = dyn_scale_target_const.i16x4
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gv1 = dyn_scale_target_const.i8x8
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dt0 = i16x4*gv0
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dt1 = i8x8*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = snarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.4h, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; sqxtn v0.8b, v4.8h
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; ret
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function %snarrow_i16x8(i16) -> i8x16 {
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gv0 = dyn_scale_target_const.i16x8
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gv1 = dyn_scale_target_const.i8x16
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dt0 = i16x8*gv0
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dt1 = i8x16*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = snarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.8h, w0
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; sqxtn v0.8b, v6.8h
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; sqxtn2 v0.16b, v0.16b, v6.8h
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; ret
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function %snarrow_i32x2(i32) -> i16x4 {
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gv0 = dyn_scale_target_const.i32x2
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gv1 = dyn_scale_target_const.i16x4
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dt0 = i32x2*gv0
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dt1 = i16x4*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = snarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.2s, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; sqxtn v0.4h, v4.4s
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; ret
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function %snarrow_i32x4(i32) -> i16x8 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i16x8
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dt0 = i32x4*gv0
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dt1 = i16x8*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = snarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.4s, w0
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; sqxtn v0.4h, v6.4s
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; sqxtn2 v0.8h, v0.8h, v6.4s
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; ret
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function %snarrow_i64x2(i64) -> i32x4 {
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gv0 = dyn_scale_target_const.i64x2
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gv1 = dyn_scale_target_const.i32x4
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dt0 = i64x2*gv0
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dt1 = i32x4*gv0
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block0(v0: i64):
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v1 = splat.dt0 v0
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v2 = snarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.2d, x0
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; sqxtn v0.2s, v6.2d
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; sqxtn2 v0.4s, v0.4s, v6.2d
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; ret
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function %unarrow_i16x4(i16) -> i8x8 {
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gv0 = dyn_scale_target_const.i16x4
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gv1 = dyn_scale_target_const.i8x8
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dt0 = i16x4*gv0
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dt1 = i8x8*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = unarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.4h, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; sqxtun v0.8b, v4.8h
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; ret
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function %unarrow_i16x8(i16) -> i8x16 {
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gv0 = dyn_scale_target_const.i16x8
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gv1 = dyn_scale_target_const.i8x16
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dt0 = i16x8*gv0
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dt1 = i8x16*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = unarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.8h, w0
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; sqxtun v0.8b, v6.8h
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; sqxtun2 v0.16b, v0.16b, v6.8h
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; ret
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function %unarrow_i32x2(i32) -> i16x4 {
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gv0 = dyn_scale_target_const.i32x2
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gv1 = dyn_scale_target_const.i16x4
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dt0 = i32x2*gv0
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dt1 = i16x4*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = unarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.2s, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; sqxtun v0.4h, v4.4s
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; ret
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function %unarrow_i32x4(i32) -> i16x8 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i16x8
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dt0 = i32x4*gv0
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dt1 = i16x8*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = unarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.4s, w0
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; sqxtun v0.4h, v6.4s
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; sqxtun2 v0.8h, v0.8h, v6.4s
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; ret
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function %unarrow_i64x2(i64) -> i32x4 {
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gv0 = dyn_scale_target_const.i64x2
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gv1 = dyn_scale_target_const.i32x4
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dt0 = i64x2*gv0
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dt1 = i32x4*gv0
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block0(v0: i64):
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v1 = splat.dt0 v0
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v2 = unarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.2d, x0
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; sqxtun v0.2s, v6.2d
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; sqxtun2 v0.4s, v0.4s, v6.2d
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; ret
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function %uunarrow_i16x4(i16) -> i8x8 {
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gv0 = dyn_scale_target_const.i16x4
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gv1 = dyn_scale_target_const.i8x8
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dt0 = i16x4*gv0
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dt1 = i8x8*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = uunarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.4h, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; uqxtn v0.8b, v4.8h
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; ret
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function %uunarrow_i16x8(i16) -> i8x16 {
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gv0 = dyn_scale_target_const.i16x8
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gv1 = dyn_scale_target_const.i8x16
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dt0 = i16x8*gv0
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dt1 = i8x16*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = uunarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.8h, w0
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; uqxtn v0.8b, v6.8h
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; uqxtn2 v0.16b, v0.16b, v6.8h
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; ret
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function %uunarrow_i32x2(i32) -> i16x4 {
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gv0 = dyn_scale_target_const.i32x2
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gv1 = dyn_scale_target_const.i16x4
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dt0 = i32x2*gv0
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dt1 = i16x4*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = uunarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.2s, w0
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; mov v4.d[1], v4.d[1], v4.d[0]
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; uqxtn v0.4h, v4.4s
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; ret
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function %uunarrow_i32x4(i32) -> i16x8 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i16x8
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dt0 = i32x4*gv0
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dt1 = i16x8*gv0
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block0(v0: i32):
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v1 = splat.dt0 v0
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v2 = uunarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.4s, w0
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; uqxtn v0.4h, v6.4s
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; uqxtn2 v0.8h, v0.8h, v6.4s
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; ret
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function %uunarrow_i64x2(i64) -> i32x4 {
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gv0 = dyn_scale_target_const.i64x2
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gv1 = dyn_scale_target_const.i32x4
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dt0 = i64x2*gv0
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dt1 = i32x4*gv0
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block0(v0: i64):
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v1 = splat.dt0 v0
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v2 = uunarrow.dt0 v1, v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v6.2d, x0
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; uqxtn v0.2s, v6.2d
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; uqxtn2 v0.4s, v0.4s, v6.2d
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; ret
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