02ef6a02b8
* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter, and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`, and `binary_arith`). Copyright (c) 2021, Arm Limited * Re-use tests + constrict Vector assert - Re-use interpreter tests as runtests where supported. - Constrict Vector assertion. - Code style adjustments following feedback. Copyright (c) 2021, Arm Limited * Runtest `i32x4` vectors on AArch64; add `i64x2` tests Copyright (c) 2021, Arm Limited * Add `simd-` prefix to test filenames Copyright (c) 2021, Arm Limited * Return aliased `SmallVec` from `extractlanes` Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors (`i32x4`, `i64x2`, ...) to not cause heap allocations. Copyright (c) 2021, Arm Limited * Accept slice to `vectorizelanes` rather than `Vec` Copyright (c) 2021, Arm Limited
35 lines
722 B
Plaintext
35 lines
722 B
Plaintext
test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64
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function %extractlane_4(i8x16) -> i8 {
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block0(v0: i8x16):
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v1 = extractlane v0, 4
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return v1
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}
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; run: %extractlane_4([1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16]) == 5
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function %extractlane_7(i16x8) -> i16 {
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block0(v0: i16x8):
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v1 = extractlane v0, 7
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return v1
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}
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; run: %extractlane_7([65528 65529 65530 65531 65532 65533 65534 65535]) == 65535
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function %extractlane_0(i32x4) -> i32 {
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block0(v0: i32x4):
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v1 = extractlane v0, 0
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return v1
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}
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; run: %extractlane_0([0 1 2 3]) == 0
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function %extractlane_1(i64x2) -> i64 {
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block0(v0: i64x2):
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v1 = extractlane v0, 1
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return v1
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}
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; run: %extractlane_1([0 4294967297]) == 4294967297
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