Andrew Brown 6fd0451bc3 Add TargetIsa::map_dwarf_register; fixes #1471 ...

This exposes the functionality of `fde::map_reg` on the `TargetIsa` trait, avoiding compilation errors on architectures where register mapping is not yet supported. The change is conditially compiled under the `unwind` feature.

2020-04-09 09:45:20 -07:00

..

cache

Adds JIT profiling support for VTune (#819)

2020-04-02 09:04:08 -05:00

address_map.rs

Don't generate DWARF sections when no functions were compiled. (#894)

2020-02-03 14:41:29 -06:00

cache.rs

Write .debug_frame information (#53)

2020-03-11 10:22:51 -05:00

compilation.rs

wasmtime: Pass around more contexts instead of fields (#1486)

2020-04-08 19:02:49 -05:00

cranelift.rs

wasmtime: Pass around more contexts instead of fields (#1486)

2020-04-08 19:02:49 -05:00

data_structures.rs

Add TargetIsa::map_dwarf_register; fixes #1471

2020-04-09 09:45:20 -07:00

frame_layout.rs

Write .debug_frame information (#53)

2020-03-11 10:22:51 -05:00

func_environ.rs

Implement data.drop and memory.init and get the rest of the bulk memory spec tests passing (#1264)

2020-03-10 09:30:11 -05:00

lib.rs

Write .debug_frame information (#53)

2020-03-11 10:22:51 -05:00

lightbeam.rs

wasmtime: Pass around more contexts instead of fields (#1486)

2020-04-08 19:02:49 -05:00

module_environ.rs

wasmtime: Pass around more contexts instead of fields (#1486)

2020-04-08 19:02:49 -05:00

module.rs

Store module name on wasmtime_environ::Module (#1309)

2020-03-13 17:51:10 -05:00

tunables.rs

wasmtime: Pass around more contexts instead of fields (#1486)

2020-04-08 19:02:49 -05:00

vmoffsets.rs

Improve robustness of cache loading/storing (#974)

2020-02-26 16:18:02 -06:00