cdecc858b4
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
207 lines
3.3 KiB
Plaintext
207 lines
3.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64
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function %foo() {
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block0:
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return
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}
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; block0:
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; ret
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function %stack_limit_leaf_zero(i64 stack_limit) {
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block0(v0: i64):
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return
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}
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; block0:
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; ret
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function %stack_limit_gv_leaf_zero(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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block0(v0: i64):
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return
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}
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; block0:
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; ret
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function %stack_limit_call_zero(i64 stack_limit) {
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fn0 = %foo()
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block0(v0: i64):
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call fn0()
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; trap_ifc stk_ovf##(sp ult a0)
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; block0:
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; load_sym t2,%foo+0
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; callind t2
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %stack_limit_gv_call_zero(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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fn0 = %foo()
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block0(v0: i64):
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call fn0()
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; ld t6,0(a0)
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; ld t6,4(t6)
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; trap_ifc stk_ovf##(sp ult t6)
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; block0:
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; load_sym t2,%foo+0
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; callind t2
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %stack_limit(i64 stack_limit) {
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ss0 = explicit_slot 168
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block0(v0: i64):
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; andi t6,a0,176
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; trap_ifc stk_ovf##(sp ult t6)
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; add sp,-176
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; block0:
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; add sp,+176
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %huge_stack_limit(i64 stack_limit) {
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ss0 = explicit_slot 400000
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block0(v0: i64):
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; trap_ifc stk_ovf##(sp ult a0)
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; lui t5,98
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; addi t5,t5,2688
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; add t6,t5,a0
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; trap_ifc stk_ovf##(sp ult t6)
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; lui a0,98
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; addi a0,a0,2688
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; call %Probestack
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; add sp,-400000
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; block0:
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; add sp,+400000
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %limit_preamble(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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ss0 = explicit_slot 20
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block0(v0: i64):
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; ld t6,0(a0)
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; ld t6,4(t6)
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; andi t6,t6,32
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; trap_ifc stk_ovf##(sp ult t6)
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; add sp,-32
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; block0:
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; add sp,+32
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %limit_preamble_huge(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0
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gv2 = load.i64 notrap aligned gv1+4
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stack_limit = gv2
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ss0 = explicit_slot 400000
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block0(v0: i64):
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; ld t6,0(a0)
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; ld t6,4(t6)
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; trap_ifc stk_ovf##(sp ult t6)
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; lui t5,98
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; addi t5,t5,2688
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; add t6,t5,t6
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; trap_ifc stk_ovf##(sp ult t6)
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; lui a0,98
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; addi a0,a0,2688
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; call %Probestack
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; add sp,-400000
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; block0:
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; add sp,+400000
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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function %limit_preamble_huge_offset(i64 vmctx) {
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gv0 = vmctx
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gv1 = load.i64 notrap aligned gv0+400000
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stack_limit = gv1
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ss0 = explicit_slot 20
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block0(v0: i64):
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return
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}
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; add sp,-16
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; sd ra,8(sp)
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; sd fp,0(sp)
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; mv fp,sp
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; ld t6,400000(a0)
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; andi t6,t6,32
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; trap_ifc stk_ovf##(sp ult t6)
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; add sp,-32
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; block0:
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; add sp,+32
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; ld ra,8(sp)
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; ld fp,0(sp)
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; add sp,+16
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; ret
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