Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
77 lines
1.2 KiB
Plaintext
77 lines
1.2 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64
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function %atomic_store_i64(i64, i64) {
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block0(v0: i64, v1: i64):
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atomic_store.i64 v0, v1
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return
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}
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; block0:
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; atomic_store.i64 a0,(a1)
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; ret
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function %atomic_store_i64_sym(i64) {
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gv0 = symbol colocated %sym
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block0(v0: i64):
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v1 = symbol_value.i64 gv0
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atomic_store.i64 v0, v1
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return
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}
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; block0:
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; load_sym t2,%sym+0
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; atomic_store.i64 a0,(t2)
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; ret
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function %atomic_store_imm_i64(i64) {
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block0(v0: i64):
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v1 = iconst.i64 12345
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atomic_store.i64 v1, v0
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return
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}
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; block0:
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; lui t2,3
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; addi t2,t2,57
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; atomic_store.i64 t2,(a0)
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; ret
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function %atomic_store_i32(i32, i64) {
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block0(v0: i32, v1: i64):
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atomic_store.i32 v0, v1
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return
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}
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; block0:
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; atomic_store.i32 a0,(a1)
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; ret
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function %atomic_store_i32_sym(i32) {
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gv0 = symbol colocated %sym
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block0(v0: i32):
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v1 = symbol_value.i64 gv0
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atomic_store.i32 v0, v1
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return
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}
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; block0:
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; load_sym t2,%sym+0
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; atomic_store.i32 a0,(t2)
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; ret
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function %atomic_store_imm_i32(i64) {
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block0(v0: i64):
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v1 = iconst.i32 12345
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atomic_store.i32 v1, v0
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return
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}
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; block0:
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; lui t2,3
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; addi t2,t2,57
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; atomic_store.i32 t2,(a0)
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; ret
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