Jakub Krauz f6a140a662 arm32 codegen ...

This commit adds arm32 code generation for some IR insts.
Floating-point instructions are not supported, because regalloc
does not allow to represent overlapping register classes,
which are needed by VFP/Neon.

There is also no support for big-endianness, I64 and I128 types.

2020-09-22 12:49:42 +02:00

..

affinity.rs

Tweak comments in regalloc code.

2019-10-31 16:54:30 +01:00

branch_splitting.rs

Mass rename Ebb and relatives to Block (#1365)

2020-02-07 10:46:47 -06:00

coalescing.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

coloring.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

context.rs

cranelift: Only emit stack maps when a function actually uses reference types

2020-08-07 16:54:51 -07:00

diversion.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

live_value_tracker.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

liveness.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

liverange.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00

mod.rs

Rename "Stackmap" to "StackMap"

2020-08-07 10:08:44 -07:00

pressure.rs

arm32 codegen

2020-09-22 12:49:42 +02:00

register_set.rs

Always use extern crate std in cranelift-codegen

2019-10-02 11:50:44 -07:00

reload.rs

Mass rename Ebb and relatives to Block (#1365)

2020-02-07 10:46:47 -06:00

safepoint.rs

Rename "Stackmap" to "StackMap"

2020-08-07 10:08:44 -07:00

solver.rs

arm32 codegen

2020-09-22 12:49:42 +02:00

spilling.rs

Fixes #1240: Add a new accessor to indicate that an opcode requires spilling all registers;

2020-03-23 12:19:28 +01:00

virtregs.rs

Rename 'an block' to 'a block'

2020-03-03 13:21:13 -06:00