0974b4a6e2
Make sure that spill instructions are generated in the same way everywhere, including adding encoding and updating live ranges.
65 lines
1.6 KiB
Plaintext
65 lines
1.6 KiB
Plaintext
test regalloc
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; Test the spiler on an ISA with few registers.
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; RV32E has 16 registers, where:
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; - %x0 is hardwired to zero.
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; - %x1 is the return address.
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; - %x2 is the stack pointer.
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; - %x3 is the global pointer.
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; - %x4 is the thread pointer.
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; - %x10-%x15 are function arguments.
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;
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; regex: V=v\d+
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isa riscv enable_e
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; In straight-line code, the first value defined is spilled.
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; That is in order:
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; 1. The argument v1.
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; 2. The link register.
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; 3. The first computed value, v2
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function %pyramid(i32) -> i32 {
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ebb0(v1: i32):
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; check: $ebb0($(rv1=$V): i32, $(rlink=$V): i32)
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; check: $v1 = spill $rv1
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; nextln: $(link=$V) = spill $rlink
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; not: spill
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v2 = iadd_imm v1, 12
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; check: $(r1v2=$V) = iadd_imm
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; nextln: $v2 = spill $r1v2
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; not: spill
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v3 = iadd_imm v2, 12
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v4 = iadd_imm v3, 12
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v5 = iadd_imm v4, 12
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v6 = iadd_imm v5, 12
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v7 = iadd_imm v6, 12
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v8 = iadd_imm v7, 12
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v9 = iadd_imm v8, 12
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v10 = iadd_imm v9, 12
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v11 = iadd_imm v10, 12
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v12 = iadd_imm v11, 12
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v13 = iadd_imm v12, 12
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v14 = iadd_imm v13, 12
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v33 = iadd v13, v14
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; check: iadd $v13
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v32 = iadd v33, v12
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v31 = iadd v32, v11
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v30 = iadd v31, v10
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v29 = iadd v30, v9
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v28 = iadd v29, v8
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v27 = iadd v28, v7
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v26 = iadd v27, v6
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v25 = iadd v26, v5
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v24 = iadd v25, v4
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v23 = iadd v24, v3
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v22 = iadd v23, v2
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; check: $(r2v2=$V) = fill $v2
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; check: $v22 = iadd $v23, $r2v2
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v21 = iadd v22, v1
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; check: $(r2v1=$V) = fill $v1
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; check: $v21 = iadd $v22, $r2v1
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; check: $(rlink2=$V) = fill $link
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return v21
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; check: return $v21, $rlink2
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}
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