9e4ab7dc86
To keep cross-compiling straightforward, Cretonne shouldn't have any behavior that depends on the host. This renames the "Native" calling convention to "SystemV", which has a defined meaning for each target, so that it's clear that the calling convention doesn't change depending on what host Cretonne is running on.
102 lines
4.4 KiB
Plaintext
102 lines
4.4 KiB
Plaintext
test regalloc
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set is_64bit
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isa intel haswell
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function %pr227(i32 [%rdi], i32 [%rsi], i32 [%rdx], i32 [%rcx], i64 vmctx [%r8]) system_v {
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gv0 = vmctx
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heap0 = static gv0, min 0, bound 0x0001_0000_0000, guard 0x8000_0000
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ebb0(v0: i32, v1: i32, v2: i32, v3: i32, v4: i64):
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@0001 [RexOp1puid#b8] v5 = iconst.i32 0
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@0003 [RexOp1puid#b8] v6 = iconst.i32 0
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@0005 [RexOp1tjccb#74] brz v6, ebb10
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@0007 [RexOp1jmpb#eb] jump ebb3(v5, v5, v5, v5, v5, v5, v0, v1, v2, v3)
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ebb3(v15: i32, v17: i32, v25: i32, v31: i32, v40: i32, v47: i32, v54: i32, v61: i32, v68: i32, v75: i32):
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@000b [RexOp1jmpb#eb] jump ebb6
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ebb6:
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@000d [RexOp1puid#b8] v8 = iconst.i32 0
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@000f [RexOp1tjccb#75] brnz v8, ebb5
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@0011 [RexOp1puid#b8] v9 = iconst.i32 0
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@0015 [RexOp1puid#b8] v11 = iconst.i32 0
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@0017 [RexOp1icscc#39] v12 = icmp.i32 eq v15, v11
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@0017 [RexOp2urm_noflags#4b6] v13 = bint.i32 v12
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@001a [RexOp1rr#21] v14 = band v9, v13
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@001b [RexOp1tjccb#75] brnz v14, ebb6
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@001d [RexOp1jmpb#eb] jump ebb7
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ebb7:
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@0020 [RexOp1tjccb#74] brz.i32 v17, ebb8
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@0022 [RexOp1puid#b8] v18 = iconst.i32 0
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@0024 [RexOp1tjccb#74] brz v18, ebb9
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@0028 [RexOp1puid#b8] v21 = iconst.i32 0
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@002a [RexOp1umr#89] v79 = uextend.i64 v5
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@002a [RexOp1rib#8083] v80 = iadd_imm.i64 v4, 0
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@002a [RexOp1ld#808b] v81 = load.i64 v80
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@002a [RexOp1rr#8001] v22 = iadd v81, v79
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@002a [RexMp1st#189] istore16 v21, v22
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@002d [RexOp1jmpb#eb] jump ebb9
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ebb9:
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@002e [RexOp1jmpb#eb] jump ebb8
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ebb8:
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@0033 [RexOp1puid#b8] v27 = iconst.i32 3
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@0035 [RexOp1puid#b8] v28 = iconst.i32 4
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@003b [RexOp1rr#09] v35 = bor.i32 v31, v13
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@003c [RexOp1tjccb#75] brnz v35, ebb15(v27)
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@003c [RexOp1jmpb#eb] jump ebb15(v28)
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ebb15(v36: i32):
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@003f [RexOp1jmpb#eb] jump ebb3(v25, v36, v25, v31, v40, v47, v54, v61, v68, v75)
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ebb5:
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@0042 [RexOp1jmpb#eb] jump ebb4
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ebb4:
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@0045 [RexOp1jmpb#eb] jump ebb2(v40, v47, v54, v61, v68, v75)
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ebb10:
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@0046 [RexOp1puid#b8] v43 = iconst.i32 0
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@0048 [RexOp1jmpb#eb] jump ebb2(v43, v5, v0, v1, v2, v3)
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ebb2(v7: i32, v45: i32, v52: i32, v59: i32, v66: i32, v73: i32):
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@004c [RexOp1puid#b8] v44 = iconst.i32 0
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@004e [RexOp1tjccb#74] brz v44, ebb12
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@0052 [RexOp1puid#b8] v50 = iconst.i32 11
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@0054 [RexOp1tjccb#74] brz v50, ebb14
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@0058 [RexOp1umr#89] v82 = uextend.i64 v52
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@0058 [RexOp1rib#8083] v83 = iadd_imm.i64 v4, 0
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@0058 [RexOp1ld#808b] v84 = load.i64 v83
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@0058 [RexOp1rr#8001] v57 = iadd v84, v82
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@0058 [RexOp1ld#8b] v58 = load.i32 v57
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@005d [RexOp1umr#89] v85 = uextend.i64 v58
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@005d [RexOp1rib#8083] v86 = iadd_imm.i64 v4, 0
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@005d [RexOp1ld#808b] v87 = load.i64 v86
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@005d [RexOp1rr#8001] v64 = iadd v87, v85
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@005d [RexOp1st#88] istore8 v59, v64
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@0060 [RexOp1puid#b8] v65 = iconst.i32 0
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@0062 [RexOp1jmpb#eb] jump ebb13(v65)
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ebb14:
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@0065 [RexOp1jmpb#eb] jump ebb13(v66)
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ebb13(v51: i32):
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@0066 [RexOp1umr#89] v88 = uextend.i64 v45
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@0066 [RexOp1rib#8083] v89 = iadd_imm.i64 v4, 0
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@0066 [RexOp1ld#808b] v90 = load.i64 v89
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@0066 [RexOp1rr#8001] v71 = iadd v90, v88
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@0066 [RexOp1st#89] store v51, v71
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@0069 [RexOp1jmpb#eb] jump ebb12
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ebb12:
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@006a [RexOp1jmpb#eb] jump ebb11
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ebb11:
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@006e [RexOp1jmpb#eb] jump ebb1
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ebb1:
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@006e [Op1ret#c3] return
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}
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