0243b642e3
This does a lot at once, since there was no clear way to split the three commits: - Instruction need to be passed an explicit InstructionFormat, - InstructionFormat deduplication is checked once all entities have been defined;
85 lines
2.5 KiB
Rust
85 lines
2.5 KiB
Rust
use crate::cdsl::cpu_modes::CpuMode;
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use crate::cdsl::instructions::{InstructionGroupBuilder, InstructionPredicateMap};
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use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::recipes::Recipes;
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use crate::cdsl::regs::{IsaRegs, IsaRegsBuilder, RegBankBuilder, RegClassBuilder};
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use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
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use crate::shared::Definitions as SharedDefinitions;
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fn define_settings(_shared: &SettingGroup) -> SettingGroup {
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let setting = SettingGroupBuilder::new("arm32");
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setting.build()
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}
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fn define_regs() -> IsaRegs {
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let mut regs = IsaRegsBuilder::new();
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let builder = RegBankBuilder::new("FloatRegs", "s")
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.units(64)
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.track_pressure(true);
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let float_regs = regs.add_bank(builder);
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let builder = RegBankBuilder::new("IntRegs", "r")
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.units(16)
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.track_pressure(true);
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let int_regs = regs.add_bank(builder);
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let builder = RegBankBuilder::new("FlagRegs", "")
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.units(1)
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.names(vec!["nzcv"])
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.track_pressure(false);
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let flag_reg = regs.add_bank(builder);
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let builder = RegClassBuilder::new_toplevel("S", float_regs).count(32);
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regs.add_class(builder);
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let builder = RegClassBuilder::new_toplevel("D", float_regs).width(2);
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regs.add_class(builder);
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let builder = RegClassBuilder::new_toplevel("Q", float_regs).width(4);
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regs.add_class(builder);
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let builder = RegClassBuilder::new_toplevel("GPR", int_regs);
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regs.add_class(builder);
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let builder = RegClassBuilder::new_toplevel("FLAG", flag_reg);
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regs.add_class(builder);
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regs.build()
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}
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pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = define_settings(&shared_defs.settings);
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let regs = define_regs();
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let inst_group = InstructionGroupBuilder::new(&mut shared_defs.all_instructions).build();
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// CPU modes for 32-bit ARM and Thumb2.
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let mut a32 = CpuMode::new("A32");
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let mut t32 = CpuMode::new("T32");
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// TODO refine these.
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let narrow_flags = shared_defs.transform_groups.by_name("narrow_flags");
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a32.legalize_default(narrow_flags);
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t32.legalize_default(narrow_flags);
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let cpu_modes = vec![a32, t32];
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// TODO implement arm32 recipes.
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let recipes = Recipes::new();
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// TODO implement arm32 encodings and predicates.
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let encodings_predicates = InstructionPredicateMap::new();
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TargetIsa::new(
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"arm32",
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inst_group,
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settings,
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regs,
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recipes,
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cpu_modes,
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encodings_predicates,
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)
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}
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