07e1f682d0
* Added Intel x86-64 encodings for 64bit loads and store instructions * Using GPR registers instead of ABCD for istore8 with REX prefix Fixed testing of 64bit intel encoding * Emit REX and REX-less encodings for optional REX prefix Value renumbering in binary64.cton
315 lines
10 KiB
Python
315 lines
10 KiB
Python
"""
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Intel Encodings.
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"""
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from __future__ import absolute_import
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from cdsl.predicates import IsUnsignedInt
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from base import instructions as base
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from base.formats import UnaryImm
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from .defs import I32, I64
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from . import recipes as r
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from . import settings as cfg
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from . import instructions as x86
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from .legalize import intel_expand
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from base.legalize import narrow, expand
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try:
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from typing import TYPE_CHECKING
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if TYPE_CHECKING:
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from cdsl.instructions import MaybeBoundInst # noqa
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except ImportError:
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pass
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I32.legalize_type(
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default=narrow,
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i32=intel_expand,
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f32=expand,
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f64=expand)
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I64.legalize_type(
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default=narrow,
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i32=intel_expand,
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i64=intel_expand,
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f32=expand,
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f64=expand)
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#
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# Helper functions for generating encodings.
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#
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def enc_i32_i64(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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"""
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Add encodings for `inst.i32` to I32.
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Add encodings for `inst.i32` to I64 with and without REX.
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Add encodings for `inst.i64` to I64 with a REX.W prefix.
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"""
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I32.enc(inst.i32, *recipe(*args, **kwargs))
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# REX-less encoding must come after REX encoding so we don't use it by
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# default. Otherwise reg-alloc would never use r8 and up.
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I64.enc(inst.i32, *recipe.rex(*args, **kwargs))
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I64.enc(inst.i32, *recipe(*args, **kwargs))
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I64.enc(inst.i64, *recipe.rex(*args, w=1, **kwargs))
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def enc_i32_i64_ld_st(inst, w_bit, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, bool, r.TailRecipe, *int, **int) -> None
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"""
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Add encodings for `inst.i32` to I32.
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Add encodings for `inst.i32` to I64 with and without REX.
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Add encodings for `inst.i64` to I64 with a REX prefix, using the `w_bit`
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argument to determine wheter or not to set the REX.W bit.
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"""
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I32.enc(inst.i32.any, *recipe(*args, **kwargs))
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# REX-less encoding must come after REX encoding so we don't use it by
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# default. Otherwise reg-alloc would never use r8 and up.
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I64.enc(inst.i32.any, *recipe.rex(*args, **kwargs))
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I64.enc(inst.i32.any, *recipe(*args, **kwargs))
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if w_bit:
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I64.enc(inst.i64.any, *recipe.rex(*args, w=1, **kwargs))
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else:
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I64.enc(inst.i64.any, *recipe.rex(*args, **kwargs))
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I64.enc(inst.i64.any, *recipe(*args, **kwargs))
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def enc_flt(inst, recipe, *args, **kwargs):
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# type: (MaybeBoundInst, r.TailRecipe, *int, **int) -> None
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"""
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Add encodings for floating point instruction `inst` to both I32 and I64.
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"""
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I32.enc(inst, *recipe(*args, **kwargs))
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I64.enc(inst, *recipe.rex(*args, **kwargs))
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I64.enc(inst, *recipe(*args, **kwargs))
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for inst, opc in [
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(base.iadd, 0x01),
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(base.isub, 0x29),
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(base.band, 0x21),
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(base.bor, 0x09),
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(base.bxor, 0x31)]:
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enc_i32_i64(inst, r.rr, opc)
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enc_i32_i64(base.imul, r.rrx, 0x0f, 0xaf)
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enc_i32_i64(x86.sdivmodx, r.div, 0xf7, rrr=7)
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enc_i32_i64(x86.udivmodx, r.div, 0xf7, rrr=6)
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enc_i32_i64(base.copy, r.umr, 0x89)
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enc_i32_i64(base.regmove, r.rmov, 0x89)
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, rrr in [
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(base.iadd_imm, 0),
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(base.band_imm, 4),
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(base.bor_imm, 1),
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(base.bxor_imm, 6)]:
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enc_i32_i64(inst, r.rib, 0x83, rrr=rrr)
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enc_i32_i64(inst, r.rid, 0x81, rrr=rrr)
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# TODO: band_imm.i64 with an unsigned 32-bit immediate can be encoded as
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# band_imm.i32. Can even use the single-byte immediate for 0xffff_ffXX masks.
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# Immediate constants.
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I32.enc(base.iconst.i32, *r.puid(0xb8))
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I64.enc(base.iconst.i32, *r.puid.rex(0xb8))
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I64.enc(base.iconst.i32, *r.puid(0xb8))
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# The 32-bit immediate movl also zero-extends to 64 bits.
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I64.enc(base.iconst.i64, *r.puid.rex(0xb8),
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instp=IsUnsignedInt(UnaryImm.imm, 32))
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I64.enc(base.iconst.i64, *r.puid(0xb8),
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instp=IsUnsignedInt(UnaryImm.imm, 32))
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# Sign-extended 32-bit immediate.
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I64.enc(base.iconst.i64, *r.uid.rex(0xc7, rrr=0, w=1))
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# Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix.
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I64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1))
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# Shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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for inst, rrr in [
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(base.rotl, 0),
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(base.rotr, 1),
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(base.ishl, 4),
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(base.ushr, 5),
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(base.sshr, 7)]:
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I32.enc(inst.i32.any, *r.rc(0xd3, rrr=rrr))
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I64.enc(inst.i64.any, *r.rc.rex(0xd3, rrr=rrr, w=1))
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I64.enc(inst.i32.any, *r.rc.rex(0xd3, rrr=rrr))
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I64.enc(inst.i32.any, *r.rc(0xd3, rrr=rrr))
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# Population count.
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I32.enc(base.popcnt.i32, *r.urm(0xf3, 0x0f, 0xb8), isap=cfg.use_popcnt)
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I64.enc(base.popcnt.i64, *r.urm.rex(0xf3, 0x0f, 0xb8, w=1),
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isap=cfg.use_popcnt)
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I64.enc(base.popcnt.i32, *r.urm.rex(0xf3, 0x0f, 0xb8), isap=cfg.use_popcnt)
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I64.enc(base.popcnt.i32, *r.urm(0xf3, 0x0f, 0xb8), isap=cfg.use_popcnt)
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# Count leading zero bits.
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I32.enc(base.clz.i32, *r.urm(0xf3, 0x0f, 0xbd), isap=cfg.use_lzcnt)
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I64.enc(base.clz.i64, *r.urm.rex(0xf3, 0x0f, 0xbd, w=1),
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isap=cfg.use_lzcnt)
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I64.enc(base.clz.i32, *r.urm.rex(0xf3, 0x0f, 0xbd), isap=cfg.use_lzcnt)
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I64.enc(base.clz.i32, *r.urm(0xf3, 0x0f, 0xbd), isap=cfg.use_lzcnt)
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# Count trailing zero bits.
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I32.enc(base.ctz.i32, *r.urm(0xf3, 0x0f, 0xbc), isap=cfg.use_bmi1)
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I64.enc(base.ctz.i64, *r.urm.rex(0xf3, 0x0f, 0xbc, w=1),
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isap=cfg.use_bmi1)
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I64.enc(base.ctz.i32, *r.urm.rex(0xf3, 0x0f, 0xbc), isap=cfg.use_bmi1)
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I64.enc(base.ctz.i32, *r.urm(0xf3, 0x0f, 0xbc), isap=cfg.use_bmi1)
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#
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# Loads and stores.
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#
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enc_i32_i64_ld_st(base.store, True, r.st, 0x89)
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enc_i32_i64_ld_st(base.store, True, r.stDisp8, 0x89)
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enc_i32_i64_ld_st(base.store, True, r.stDisp32, 0x89)
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I64.enc(base.istore32.i64.any, *r.st.rex(0x89))
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I64.enc(base.istore32.i64.any, *r.stDisp8.rex(0x89))
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I64.enc(base.istore32.i64.any, *r.stDisp32.rex(0x89))
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enc_i32_i64_ld_st(base.istore16, False, r.st, 0x66, 0x89)
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enc_i32_i64_ld_st(base.istore16, False, r.stDisp8, 0x66, 0x89)
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enc_i32_i64_ld_st(base.istore16, False, r.stDisp32, 0x66, 0x89)
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# Byte stores are more complicated because the registers they can address
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# depends of the presence of a REX prefix
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I32.enc(base.istore8.i32.any, *r.st_abcd(0x88))
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I64.enc(base.istore8.i32.any, *r.st_abcd(0x88))
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I64.enc(base.istore8.i64.any, *r.st.rex(0x88))
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I32.enc(base.istore8.i32.any, *r.stDisp8_abcd(0x88))
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I64.enc(base.istore8.i32.any, *r.stDisp8_abcd(0x88))
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I64.enc(base.istore8.i64.any, *r.stDisp8.rex(0x88))
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I32.enc(base.istore8.i32.any, *r.stDisp32_abcd(0x88))
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I64.enc(base.istore8.i32.any, *r.stDisp32_abcd(0x88))
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I64.enc(base.istore8.i64.any, *r.stDisp32.rex(0x88))
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enc_i32_i64_ld_st(base.load, True, r.ld, 0x8b)
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enc_i32_i64_ld_st(base.load, True, r.ldDisp8, 0x8b)
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enc_i32_i64_ld_st(base.load, True, r.ldDisp32, 0x8b)
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I64.enc(base.uload32.i64, *r.ld.rex(0x8b))
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I64.enc(base.uload32.i64, *r.ldDisp8.rex(0x8b))
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I64.enc(base.uload32.i64, *r.ldDisp32.rex(0x8b))
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I64.enc(base.sload32.i64, *r.ld.rex(0x63, w=1))
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I64.enc(base.sload32.i64, *r.ldDisp8.rex(0x63, w=1))
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I64.enc(base.sload32.i64, *r.ldDisp32.rex(0x63, w=1))
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enc_i32_i64_ld_st(base.uload16, True, r.ld, 0x0f, 0xb7)
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enc_i32_i64_ld_st(base.uload16, True, r.ldDisp8, 0x0f, 0xb7)
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enc_i32_i64_ld_st(base.uload16, True, r.ldDisp32, 0x0f, 0xb7)
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enc_i32_i64_ld_st(base.sload16, True, r.ld, 0x0f, 0xbf)
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enc_i32_i64_ld_st(base.sload16, True, r.ldDisp8, 0x0f, 0xbf)
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enc_i32_i64_ld_st(base.sload16, True, r.ldDisp32, 0x0f, 0xbf)
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enc_i32_i64_ld_st(base.uload8, True, r.ld, 0x0f, 0xb6)
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enc_i32_i64_ld_st(base.uload8, True, r.ldDisp8, 0x0f, 0xb6)
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enc_i32_i64_ld_st(base.uload8, True, r.ldDisp32, 0x0f, 0xb6)
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enc_i32_i64_ld_st(base.sload8, True, r.ld, 0x0f, 0xbe)
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enc_i32_i64_ld_st(base.sload8, True, r.ldDisp8, 0x0f, 0xbe)
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enc_i32_i64_ld_st(base.sload8, True, r.ldDisp32, 0x0f, 0xbe)
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#
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# Call/return
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#
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I32.enc(base.call, *r.call_id(0xe8))
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I32.enc(base.call_indirect.i32, *r.call_r(0xff, rrr=2))
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I32.enc(base.x_return, *r.ret(0xc3))
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I64.enc(base.x_return, *r.ret(0xc3))
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#
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# Branches
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#
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I32.enc(base.jump, *r.jmpb(0xeb))
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I32.enc(base.jump, *r.jmpd(0xe9))
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I64.enc(base.jump, *r.jmpb(0xeb))
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I64.enc(base.jump, *r.jmpd(0xe9))
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enc_i32_i64(base.brz, r.tjccb, 0x74)
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enc_i32_i64(base.brnz, r.tjccb, 0x75)
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#
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# Trap as ud2
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#
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I32.enc(base.trap, *r.noop(0x0f, 0x0b))
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I64.enc(base.trap, *r.noop(0x0f, 0x0b))
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#
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# Comparisons
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#
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enc_i32_i64(base.icmp, r.icscc, 0x39)
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#
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# Convert bool to int.
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#
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# This assumes that b1 is represented as an 8-bit low register with the value 0
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# or 1.
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I32.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
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I64.enc(base.bint.i64.b1, *r.urm.rex(0x0f, 0xb6, w=1))
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I64.enc(base.bint.i64.b1, *r.urm_abcd(0x0f, 0xb6)) # zext to i64 implicit.
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I64.enc(base.bint.i32.b1, *r.urm.rex(0x0f, 0xb6))
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I64.enc(base.bint.i32.b1, *r.urm_abcd(0x0f, 0xb6))
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# Numerical conversions.
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# Converting i64 to i32 is a no-op in 64-bit mode.
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I64.enc(base.ireduce.i32.i64, r.null, 0)
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I64.enc(base.sextend.i64.i32, *r.urm.rex(0x63, w=1))
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# A 32-bit register copy clears the high 32 bits.
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I64.enc(base.uextend.i64.i32, *r.umr.rex(0x89))
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I64.enc(base.uextend.i64.i32, *r.umr(0x89))
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#
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# Floating point
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#
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# movd
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enc_flt(base.bitcast.f32.i32, r.frurm, 0x66, 0x0f, 0x6e)
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enc_flt(base.bitcast.i32.f32, r.rfumr, 0x66, 0x0f, 0x7e)
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# movq
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I64.enc(base.bitcast.f64.i64, *r.frurm.rex(0x66, 0x0f, 0x6e, w=1))
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I64.enc(base.bitcast.i64.f64, *r.rfumr.rex(0x66, 0x0f, 0x7e, w=1))
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# cvtsi2ss
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enc_i32_i64(base.fcvt_from_sint.f32, r.frurm, 0xf3, 0x0f, 0x2a)
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# cvtsi2sd
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enc_i32_i64(base.fcvt_from_sint.f64, r.frurm, 0xf2, 0x0f, 0x2a)
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# cvtss2sd
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enc_flt(base.fpromote.f64.f32, r.furm, 0xf3, 0x0f, 0x5a)
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# cvtsd2ss
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enc_flt(base.fdemote.f32.f64, r.furm, 0xf2, 0x0f, 0x5a)
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# Binary arithmetic ops.
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for inst, opc in [
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(base.fadd, 0x58),
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(base.fsub, 0x5c),
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(base.fmul, 0x59),
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(base.fdiv, 0x5e)]:
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enc_flt(inst.f32, r.frm, 0xf3, 0x0f, opc)
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enc_flt(inst.f64, r.frm, 0xf2, 0x0f, opc)
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# Binary bitwise ops.
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for inst, opc in [
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(base.band, 0x54),
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(base.band_not, 0x55),
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(base.bor, 0x56),
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(base.bxor, 0x57)]:
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enc_flt(inst.f32, r.frm, 0x0f, opc)
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enc_flt(inst.f64, r.frm, 0x0f, opc)
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