ffe89cdc0a
EFLAGS is a subregister of RFLAGS. For consistency with GPRs where we use the 64-bit names to refer to the registers, use the 64-bit name for RFLAGS as well.
90 lines
2.4 KiB
Plaintext
90 lines
2.4 KiB
Plaintext
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test binemit
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set is_64bit
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set is_compressed
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isa intel baseline
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/baseline_clz_ctz_popcount_encoding.cton | llvm-mc -show-encoding -triple=x86_64
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;
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function %Foo() {
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ebb0:
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; 64-bit wide bsf
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[-,%r11] v10 = iconst.i64 0x1234
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; asm: bsfq %r11, %rcx
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[-,%rcx,%rflags] v11, v12 = x86_bsf v10 ; bin: 49 0f bc cb
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[-,%rdx] v14 = iconst.i64 0x5678
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; asm: bsfq %rdx, %r12
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[-,%r12,%rflags] v15, v16 = x86_bsf v14 ; bin: 4c 0f bc e2
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; asm: bsfq %rdx, %rdi
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[-,%rdi,%rflags] v17, v18 = x86_bsf v14 ; bin: 48 0f bc fa
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; 32-bit wide bsf
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[-,%r11] v20 = iconst.i32 0x1234
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; asm: bsfl %r11d, %ecx
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[-,%rcx,%rflags] v21, v22 = x86_bsf v20 ; bin: 41 0f bc cb
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[-,%rdx] v24 = iconst.i32 0x5678
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; asm: bsfl %edx, %r12d
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[-,%r12,%rflags] v25, v26 = x86_bsf v24 ; bin: 44 0f bc e2
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; asm: bsfl %edx, %esi
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[-,%rsi,%rflags] v27, v28 = x86_bsf v24 ; bin: 0f bc f2
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; 64-bit wide bsr
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[-,%r11] v30 = iconst.i64 0x1234
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; asm: bsrq %r11, %rcx
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[-,%rcx,%rflags] v31, v32 = x86_bsr v30 ; bin: 49 0f bd cb
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[-,%rdx] v34 = iconst.i64 0x5678
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; asm: bsrq %rdx, %r12
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[-,%r12,%rflags] v35, v36 = x86_bsr v34 ; bin: 4c 0f bd e2
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; asm: bsrq %rdx, %rdi
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[-,%rdi,%rflags] v37, v38 = x86_bsr v34 ; bin: 48 0f bd fa
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; 32-bit wide bsr
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[-,%r11] v40 = iconst.i32 0x1234
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; asm: bsrl %r11d, %ecx
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[-,%rcx,%rflags] v41, v42 = x86_bsr v40 ; bin: 41 0f bd cb
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[-,%rdx] v44 = iconst.i32 0x5678
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; asm: bsrl %edx, %r12d
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[-,%r12,%rflags] v45, v46 = x86_bsr v44 ; bin: 44 0f bd e2
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; asm: bsrl %edx, %esi
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[-,%rsi,%rflags] v47, v48 = x86_bsr v44 ; bin: 0f bd f2
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; 64-bit wide cmov
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; asm: cmoveq %r11, %rdx
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[-,%rdx] v51 = selectif.i64 eq v48, v30, v34 ; bin: 49 0f 44 d3
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; asm: cmoveq %rdi, %rdx
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[-,%rdx] v52 = selectif.i64 eq v48, v37, v34 ; bin: 48 0f 44 d7
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; 32-bit wide cmov
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; asm: cmovnel %r11d, %edx
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[-,%rdx] v60 = selectif.i32 ne v48, v40, v44 ; bin: 41 0f 45 d3
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; asm: cmovlel %esi, %edx
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[-,%rdx] v61 = selectif.i32 sle v48, v27, v44 ; bin: 0f 4e d6
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trap user0
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}
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