eabd43a178
* cranelift: Add `adrp` encoding to AArch64 backend * cranelift: Support GOT Symbol References in AArch64 * cranelift: Add MachO GOT relocations * cranelift: Do not mark the GOT PageOffset12 MachO relocation as relative
132 lines
5.5 KiB
Rust
132 lines
5.5 KiB
Rust
//! Binary machine code emission.
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//!
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//! The `binemit` module contains code for translating Cranelift's intermediate representation into
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//! binary machine code.
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mod stack_map;
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pub use self::stack_map::StackMap;
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use core::fmt;
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#[cfg(feature = "enable-serde")]
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use serde::{Deserialize, Serialize};
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/// Offset in bytes from the beginning of the function.
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///
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/// Cranelift can be used as a cross compiler, so we don't want to use a type like `usize` which
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/// depends on the *host* platform, not the *target* platform.
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pub type CodeOffset = u32;
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/// Addend to add to the symbol value.
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pub type Addend = i64;
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/// Relocation kinds for every ISA
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "enable-serde", derive(Serialize, Deserialize))]
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pub enum Reloc {
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/// absolute 4-byte
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Abs4,
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/// absolute 8-byte
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Abs8,
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/// x86 PC-relative 4-byte
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X86PCRel4,
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/// x86 call to PC-relative 4-byte
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X86CallPCRel4,
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/// x86 call to PLT-relative 4-byte
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X86CallPLTRel4,
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/// x86 GOT PC-relative 4-byte
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X86GOTPCRel4,
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/// The 32-bit offset of the target from the beginning of its section.
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/// Equivalent to `IMAGE_REL_AMD64_SECREL`.
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/// See: [PE Format](https://docs.microsoft.com/en-us/windows/win32/debug/pe-format)
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X86SecRel,
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/// Arm32 call target
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Arm32Call,
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/// Arm64 call target. Encoded as bottom 26 bits of instruction. This
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/// value is sign-extended, multiplied by 4, and added to the PC of
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/// the call instruction to form the destination address.
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Arm64Call,
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/// s390x PC-relative 4-byte offset
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S390xPCRel32Dbl,
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/// s390x PC-relative 4-byte offset to PLT
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S390xPLTRel32Dbl,
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/// Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
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ElfX86_64TlsGd,
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/// Mach-O x86_64 32 bit signed PC relative offset to a `__thread_vars` entry.
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MachOX86_64Tlv,
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/// AArch64 TLS GD
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/// Set an ADRP immediate field to the top 21 bits of the final address. Checks for overflow.
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/// This is equivalent to `R_AARCH64_TLSGD_ADR_PAGE21` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage)
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Aarch64TlsGdAdrPage21,
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/// AArch64 TLS GD
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/// Set the add immediate field to the low 12 bits of the final address. Does not check for overflow.
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/// This is equivalent to `R_AARCH64_TLSGD_ADD_LO12_NC` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage)
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Aarch64TlsGdAddLo12Nc,
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/// AArch64 GOT Page
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/// Set the immediate value of an ADRP to bits 32:12 of X; check that –232 <= X < 232
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/// This is equivalent to `R_AARCH64_ADR_GOT_PAGE` (311) in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#static-aarch64-relocations)
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Aarch64AdrGotPage21,
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/// AArch64 GOT Low bits
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/// Set the LD/ST immediate field to bits 11:3 of X. No overflow check; check that X&7 = 0
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/// This is equivalent to `R_AARCH64_LD64_GOT_LO12_NC` (312) in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#static-aarch64-relocations)
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Aarch64Ld64GotLo12Nc,
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/// procedure call.
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/// call symbol
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/// expands to the following assembly and relocation:
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/// auipc ra, 0
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/// jalr ra, ra, 0
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RiscvCall,
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/// s390x TLS GD64 - 64-bit offset of tls_index for GD symbol in GOT
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S390xTlsGd64,
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/// s390x TLS GDCall - marker to enable optimization of TLS calls
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S390xTlsGdCall,
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}
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impl fmt::Display for Reloc {
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/// Display trait implementation drops the arch, since its used in contexts where the arch is
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/// already unambiguous, e.g. clif syntax with isa specified. In other contexts, use Debug.
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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match *self {
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Self::Abs4 => write!(f, "Abs4"),
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Self::Abs8 => write!(f, "Abs8"),
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Self::S390xPCRel32Dbl => write!(f, "PCRel32Dbl"),
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Self::S390xPLTRel32Dbl => write!(f, "PLTRel32Dbl"),
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Self::X86PCRel4 => write!(f, "PCRel4"),
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Self::X86CallPCRel4 => write!(f, "CallPCRel4"),
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Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"),
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Self::X86GOTPCRel4 => write!(f, "GOTPCRel4"),
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Self::X86SecRel => write!(f, "SecRel"),
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Self::Arm32Call | Self::Arm64Call => write!(f, "Call"),
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Self::RiscvCall => write!(f, "RiscvCall"),
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Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
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Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),
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Self::Aarch64TlsGdAdrPage21 => write!(f, "Aarch64TlsGdAdrPage21"),
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Self::Aarch64TlsGdAddLo12Nc => write!(f, "Aarch64TlsGdAddLo12Nc"),
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Self::Aarch64AdrGotPage21 => write!(f, "Aarch64AdrGotPage21"),
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Self::Aarch64Ld64GotLo12Nc => write!(f, "Aarch64AdrGotLo12Nc"),
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Self::S390xTlsGd64 => write!(f, "TlsGd64"),
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Self::S390xTlsGdCall => write!(f, "TlsGdCall"),
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}
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}
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}
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/// Container for information about a vector of compiled code and its supporting read-only data.
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///
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/// The code starts at offset 0 and is followed optionally by relocatable jump tables and copyable
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/// (raw binary) read-only data. Any padding between sections is always part of the section that
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/// precedes the boundary between the sections.
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#[derive(Debug, PartialEq)]
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pub struct CodeInfo {
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/// Number of bytes in total.
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pub total_size: CodeOffset,
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}
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