Jakob Stoklund Olesen 9629867d0c Encodings for load/store instructions. ...

We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.

2017-05-12 16:49:39 -07:00

..

cfg

Syntax tweak: Omit comma after an initial enum immediate.

2017-04-10 10:28:37 -07:00

domtree

Implement a domtree sub-test.

2016-09-16 14:50:32 -07:00

isa

Encodings for load/store instructions.

2017-05-12 16:49:39 -07:00

parser

Add a regmove instruction.

2017-05-02 11:32:12 -07:00

regalloc

Add fixed constraints for ABI arguments and return values.

2017-05-11 12:02:02 -07:00

verifier

Add a 'test verifier' sub-test.

2016-09-16 16:25:36 -07:00