05cbd667c7
* Cranelift: use regalloc2 constraints on caller side of ABI code. This PR updates the shared ABI code and backends to use register-operand constraints rather than explicit pinned-vreg moves for register arguments and return values. The s390x backend was not updated, because it has its own implementation of ABI code. Ideally we could converge back to the code shared by x64 and aarch64 (which didn't exist when s390x ported calls to ISLE, so the current situation is underestandable, to be clear!). I'll leave this for future work. This PR exposed several places where regalloc2 needed to be a bit more flexible with constraints; it requires regalloc2#74 to be merged and pulled in. * Update to regalloc2 0.3.3. In addition to version bump, this required removing two asserts as `SpillSlot`s no longer carry their class (so we can't assert that they have the correct class). * Review comments. * Filetest updates. * Add cargo-vet audit for regalloc2 0.3.2 -> 0.3.3 upgrade. * Update to regalloc2 0.4.0.
462 lines
7.6 KiB
Plaintext
462 lines
7.6 KiB
Plaintext
test compile precise-output
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target s390x
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function %bitrev_i128(i128) -> i128 {
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block0(v0: i128):
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v1 = bitrev v0
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return v1
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}
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; block0:
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; vl %v0, 0(%r3)
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; vrepib %v5, 170
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; vrepib %v7, 1
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; vsl %v17, %v0, %v7
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; vsrl %v19, %v0, %v7
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; vsel %v21, %v17, %v19, %v5
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; vrepib %v23, 204
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; vrepib %v25, 2
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; vsl %v27, %v21, %v25
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; vsrl %v29, %v21, %v25
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; vsel %v31, %v27, %v29, %v23
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; vrepib %v1, 240
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; vrepib %v3, 4
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; vsl %v5, %v31, %v3
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; vsrl %v7, %v31, %v3
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; vsel %v17, %v5, %v7, %v1
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; bras %r1, 20 ; data.u128 0x0f0e0d0c0b0a09080706050403020100 ; vl %v19, 0(%r1)
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; vperm %v21, %v17, %v17, %v19
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; vst %v21, 0(%r2)
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; br %r14
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function %bitrev_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = bitrev v0
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return v1
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}
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; block0:
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; lgr %r3, %r2
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; llihf %r2, 2863311530
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; iilf %r2, 2863311530
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; lgr %r5, %r3
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; sllg %r4, %r5, 1
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; srlg %r3, %r5, 1
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; ngr %r4, %r2
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; xilf %r2, 4294967295
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; xihf %r2, 4294967295
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; ngrk %r2, %r3, %r2
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; ogr %r4, %r2
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; llihf %r3, 3435973836
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; iilf %r3, 3435973836
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; sllg %r5, %r4, 2
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; srlg %r4, %r4, 2
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; ngr %r5, %r3
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; xilf %r3, 4294967295
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; xihf %r3, 4294967295
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; ngrk %r3, %r4, %r3
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; ogr %r5, %r3
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; llihf %r4, 4042322160
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; iilf %r4, 4042322160
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; sllg %r2, %r5, 4
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; srlg %r5, %r5, 4
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; ngr %r2, %r4
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; xilf %r4, 4294967295
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; xihf %r4, 4294967295
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; ngrk %r4, %r5, %r4
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; ogr %r2, %r4
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; lrvgr %r2, %r2
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; br %r14
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function %bitrev_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = bitrev v0
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return v1
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}
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; block0:
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; iilf %r5, 2863311530
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; sllk %r3, %r2, 1
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; srlk %r2, %r2, 1
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; nr %r3, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r5, %r3, %r4
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; iilf %r3, 3435973836
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; sllk %r2, %r5, 2
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; srlk %r4, %r5, 2
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; nrk %r5, %r2, %r3
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; xilf %r3, 4294967295
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; nrk %r2, %r4, %r3
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; ork %r3, %r5, %r2
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; iilf %r5, 4042322160
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; sllk %r4, %r3, 4
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; srlk %r2, %r3, 4
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; nrk %r3, %r4, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r5, %r3, %r4
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; lrvr %r2, %r5
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; br %r14
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function %bitrev_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = bitrev v0
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return v1
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}
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; block0:
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; lhi %r5, -21846
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; sllk %r3, %r2, 1
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; srlk %r2, %r2, 1
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; nr %r3, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r5, %r3, %r4
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; lhi %r3, -13108
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; sllk %r2, %r5, 2
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; srlk %r4, %r5, 2
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; nrk %r5, %r2, %r3
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; xilf %r3, 4294967295
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; nrk %r2, %r4, %r3
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; ork %r3, %r5, %r2
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; lhi %r5, -3856
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; sllk %r4, %r3, 4
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; srlk %r2, %r3, 4
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; nrk %r3, %r4, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r5, %r3, %r4
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; lrvr %r3, %r5
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; srlk %r2, %r3, 16
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; br %r14
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function %bitrev_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = bitrev v0
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return v1
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}
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; block0:
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; lhi %r5, -21846
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; sllk %r3, %r2, 1
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; srlk %r2, %r2, 1
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; nr %r3, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r5, %r3, %r4
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; lhi %r3, -13108
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; sllk %r2, %r5, 2
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; srlk %r4, %r5, 2
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; nrk %r5, %r2, %r3
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; xilf %r3, 4294967295
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; nrk %r2, %r4, %r3
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; ork %r3, %r5, %r2
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; lhi %r5, -3856
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; sllk %r4, %r3, 4
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; srlk %r2, %r3, 4
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; nrk %r3, %r4, %r5
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; xilf %r5, 4294967295
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; nrk %r4, %r2, %r5
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; ork %r2, %r3, %r4
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; br %r14
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function %clz_i128(i128) -> i128 {
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block0(v0: i128):
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v1 = clz v0
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return v1
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}
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; block0:
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; vl %v0, 0(%r3)
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; vclzg %v5, %v0
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; vgbm %v7, 0
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; vpdi %v17, %v7, %v5, 0
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; vpdi %v19, %v7, %v5, 1
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; vag %v21, %v17, %v19
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; vrepig %v23, 64
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; vceqg %v25, %v17, %v23
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; vsel %v27, %v21, %v17, %v25
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; vst %v27, 0(%r2)
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; br %r14
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function %clz_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = clz v0
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return v1
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}
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; block0:
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; flogr %r0, %r2
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; lgr %r2, %r0
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; br %r14
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function %clz_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = clz v0
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return v1
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}
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; block0:
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; llgfr %r5, %r2
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; flogr %r0, %r5
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; ahik %r2, %r0, -32
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; br %r14
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function %clz_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = clz v0
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return v1
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}
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; block0:
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; llghr %r5, %r2
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; flogr %r0, %r5
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; ahik %r2, %r0, -48
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; br %r14
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function %clz_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = clz v0
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return v1
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}
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; block0:
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; llgcr %r5, %r2
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; flogr %r0, %r5
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; ahik %r2, %r0, -56
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; br %r14
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function %cls_i128(i128) -> i128 {
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block0(v0: i128):
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v1 = cls v0
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return v1
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}
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; block0:
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; vl %v0, 0(%r3)
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; vrepib %v5, 255
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; vsrab %v7, %v0, %v5
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; vsra %v17, %v7, %v5
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; vx %v19, %v0, %v17
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; vclzg %v21, %v19
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; vgbm %v23, 0
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; vpdi %v25, %v23, %v21, 0
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; vpdi %v27, %v23, %v21, 1
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; vag %v29, %v25, %v27
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; vrepig %v31, 64
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; vceqg %v1, %v25, %v31
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; vsel %v3, %v29, %v25, %v1
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; vaq %v5, %v3, %v5
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; vst %v5, 0(%r2)
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; br %r14
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function %cls_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = cls v0
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return v1
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}
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; block0:
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; srag %r5, %r2, 63
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; xgrk %r3, %r2, %r5
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; flogr %r0, %r3
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; aghik %r2, %r0, -1
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; br %r14
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function %cls_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = cls v0
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return v1
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}
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; block0:
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; lgfr %r5, %r2
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; srag %r3, %r5, 63
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; xgr %r5, %r3
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; flogr %r0, %r5
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; ahik %r2, %r0, -33
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; br %r14
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function %cls_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = cls v0
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return v1
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}
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; block0:
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; lghr %r5, %r2
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; srag %r3, %r5, 63
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; xgr %r5, %r3
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; flogr %r0, %r5
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; ahik %r2, %r0, -49
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; br %r14
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function %cls_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = cls v0
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return v1
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}
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; block0:
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; lgbr %r5, %r2
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; srag %r3, %r5, 63
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; xgr %r5, %r3
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; flogr %r0, %r5
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; ahik %r2, %r0, -57
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; br %r14
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function %ctz_i128(i128) -> i128 {
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block0(v0: i128):
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v1 = ctz v0
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return v1
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}
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; block0:
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; vl %v0, 0(%r3)
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; vctzg %v5, %v0
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; vgbm %v7, 0
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; vpdi %v17, %v7, %v5, 0
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; vpdi %v19, %v7, %v5, 1
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; vag %v21, %v17, %v19
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; vrepig %v23, 64
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; vceqg %v25, %v19, %v23
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; vsel %v27, %v21, %v19, %v25
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; vst %v27, 0(%r2)
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; br %r14
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function %ctz_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = ctz v0
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return v1
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}
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; block0:
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; lcgr %r5, %r2
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; ngrk %r3, %r2, %r5
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; flogr %r0, %r3
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; locghie %r0, -1
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; lghi %r3, 63
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; sgrk %r2, %r3, %r0
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; br %r14
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function %ctz_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = ctz v0
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return v1
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}
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; block0:
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; lgr %r5, %r2
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; oihl %r5, 1
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; lcgr %r3, %r5
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; ngr %r5, %r3
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; flogr %r0, %r5
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; lhi %r4, 63
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; srk %r2, %r4, %r0
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; br %r14
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function %ctz_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = ctz v0
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return v1
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}
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; block0:
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; lgr %r5, %r2
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; oilh %r5, 1
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; lcgr %r3, %r5
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; ngr %r5, %r3
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; flogr %r0, %r5
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; lhi %r4, 63
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; srk %r2, %r4, %r0
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; br %r14
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function %ctz_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = ctz v0
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return v1
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}
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; block0:
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; lgr %r5, %r2
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; oill %r5, 256
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; lcgr %r3, %r5
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; ngr %r5, %r3
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; flogr %r0, %r5
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; lhi %r4, 63
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; srk %r2, %r4, %r0
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; br %r14
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function %popcnt_i128(i128) -> i128 {
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block0(v0: i128):
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v1 = popcnt v0
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return v1
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}
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; block0:
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; vl %v0, 0(%r3)
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; vpopctg %v5, %v0
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; vgbm %v7, 0
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; vpdi %v17, %v7, %v5, 0
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; vpdi %v19, %v7, %v5, 1
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; vag %v21, %v17, %v19
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; vst %v21, 0(%r2)
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; br %r14
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function %popcnt_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = popcnt v0
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return v1
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}
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; block0:
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; popcnt %r5, %r2
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; sllg %r3, %r5, 32
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; agr %r5, %r3
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; sllg %r3, %r5, 16
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; agr %r5, %r3
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; sllg %r3, %r5, 8
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; agr %r5, %r3
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; srlg %r2, %r5, 56
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; br %r14
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function %popcnt_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = popcnt v0
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return v1
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}
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; block0:
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; popcnt %r5, %r2
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; sllk %r3, %r5, 16
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; ar %r5, %r3
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; sllk %r3, %r5, 8
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; ar %r5, %r3
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; srlk %r2, %r5, 24
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; br %r14
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function %popcnt_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = popcnt v0
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return v1
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}
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; block0:
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; popcnt %r5, %r2
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; srlk %r3, %r5, 8
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; ark %r2, %r5, %r3
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; nill %r2, 255
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; br %r14
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function %popcnt_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = popcnt v0
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return v1
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}
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; block0:
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; popcnt %r2, %r2
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; br %r14
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