05cbd667c7
* Cranelift: use regalloc2 constraints on caller side of ABI code. This PR updates the shared ABI code and backends to use register-operand constraints rather than explicit pinned-vreg moves for register arguments and return values. The s390x backend was not updated, because it has its own implementation of ABI code. Ideally we could converge back to the code shared by x64 and aarch64 (which didn't exist when s390x ported calls to ISLE, so the current situation is underestandable, to be clear!). I'll leave this for future work. This PR exposed several places where regalloc2 needed to be a bit more flexible with constraints; it requires regalloc2#74 to be merged and pulled in. * Update to regalloc2 0.3.3. In addition to version bump, this required removing two asserts as `SpillSlot`s no longer carry their class (so we can't assert that they have the correct class). * Review comments. * Filetest updates. * Add cargo-vet audit for regalloc2 0.3.2 -> 0.3.3 upgrade. * Update to regalloc2 0.4.0.
341 lines
5.3 KiB
Plaintext
341 lines
5.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %f5(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = iadd.i64 v0, v2
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v4 = load.i32 v3
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return v4
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}
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; block0:
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; ldr w0, [x0, w1, SXTW]
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; ret
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function %f6(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = iadd.i64 v2, v0
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v4 = load.i32 v3
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return v4
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}
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; block0:
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; ldr w0, [x0, w1, SXTW]
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; ret
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function %f7(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = uextend.i64 v0
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v3 = uextend.i64 v1
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v4 = iadd.i64 v2, v3
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v5 = load.i32 v4
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return v5
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}
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; block0:
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; mov w4, w0
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; ldr w0, [x4, w1, UXTW]
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; ret
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function %f8(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = iconst.i64 32
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v4 = iadd.i64 v2, v3
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v5 = iadd.i64 v4, v0
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v6 = iadd.i64 v5, v5
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v7 = load.i32 v6+4
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return v7
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}
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; block0:
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; add x4, x0, #68
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; add x4, x4, x0
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; add x4, x4, x1, SXTW
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; ldr w0, [x4, w1, SXTW]
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; ret
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function %f9(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i64 48
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v4 = iadd.i64 v0, v1
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v5 = iadd.i64 v4, v2
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v6 = iadd.i64 v5, v3
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v7 = load.i32 v6
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return v7
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}
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; block0:
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; mov x6, x0
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; add x6, x6, x2
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; add x6, x6, x1
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; ldr w0, [x6, #48]
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; ret
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function %f10(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i64 4100
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v4 = iadd.i64 v0, v1
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v5 = iadd.i64 v4, v2
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v6 = iadd.i64 v5, v3
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v7 = load.i32 v6
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return v7
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}
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; block0:
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; movz x5, #4100
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; add x5, x5, x1
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; add x5, x5, x2
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; ldr w0, [x5, x0]
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; ret
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function %f10() -> i32 {
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block0:
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v1 = iconst.i64 1234
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v2 = load.i32 v1
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return v2
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}
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; block0:
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; movz x1, #1234
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; ldr w0, [x1]
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; ret
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function %f11(i64) -> i32 {
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block0(v0: i64):
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v1 = iconst.i64 8388608 ;; Imm12: 0x800 << 12
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v2 = iadd.i64 v0, v1
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v3 = load.i32 v2
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return v3
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}
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; block0:
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; add x3, x0, #8388608
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; ldr w0, [x3]
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; ret
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function %f12(i64) -> i32 {
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block0(v0: i64):
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v1 = iconst.i64 -4
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v2 = iadd.i64 v0, v1
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v3 = load.i32 v2
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return v3
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}
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; block0:
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; sub x3, x0, #4
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; ldr w0, [x3]
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; ret
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function %f13(i64) -> i32 {
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block0(v0: i64):
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v1 = iconst.i64 1000000000
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v2 = iadd.i64 v0, v1
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v3 = load.i32 v2
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return v3
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}
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; block0:
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; movz w3, #51712
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; movk w3, w3, #15258, LSL #16
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; add x3, x3, x0
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; ldr w0, [x3]
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; ret
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function %f14(i32) -> i32 {
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block0(v0: i32):
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v1 = sextend.i64 v0
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v2 = load.i32 v1
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return v2
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}
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; block0:
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; sxtw x3, w0
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; ldr w0, [x3]
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; ret
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function %f15(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sextend.i64 v0
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v3 = sextend.i64 v1
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v4 = iadd.i64 v2, v3
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v5 = load.i32 v4
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return v5
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}
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; block0:
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; sxtw x4, w0
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; ldr w0, [x4, w1, SXTW]
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; ret
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function %f18(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i32 -4098
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v6 = uextend.i64 v3
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v5 = sload16.i32 v6+0
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return v5
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}
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; block0:
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; movn w5, #4097
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; ldrsh x0, [x5]
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; ret
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function %f19(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i32 4098
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v6 = uextend.i64 v3
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v5 = sload16.i32 v6+0
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return v5
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}
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; block0:
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; movz x5, #4098
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; ldrsh x0, [x5]
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; ret
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function %f20(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i32 -4098
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v6 = sextend.i64 v3
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v5 = sload16.i32 v6+0
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return v5
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}
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; block0:
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; movn w5, #4097
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; sxtw x7, w5
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; ldrsh x0, [x7]
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; ret
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function %f21(i64, i64, i64) -> i32 {
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block0(v0: i64, v1: i64, v2: i64):
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v3 = iconst.i32 4098
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v6 = sextend.i64 v3
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v5 = sload16.i32 v6+0
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return v5
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}
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; block0:
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; movz x5, #4098
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; sxtw x7, w5
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; ldrsh x0, [x7]
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; ret
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function %i128(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0
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store.i128 v1, v0
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return v1
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}
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; block0:
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; mov x8, x0
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; mov x6, x8
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; ldp x0, x1, [x6]
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; mov x7, x8
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; stp x0, x1, [x7]
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; ret
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function %i128_imm_offset(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0+16
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store.i128 v1, v0+16
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return v1
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}
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; block0:
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; mov x8, x0
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; mov x6, x8
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; ldp x0, x1, [x6, #16]
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; mov x7, x8
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; stp x0, x1, [x7, #16]
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; ret
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function %i128_imm_offset_large(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0+504
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store.i128 v1, v0+504
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return v1
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}
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; block0:
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; mov x8, x0
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; mov x6, x8
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; ldp x0, x1, [x6, #504]
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; mov x7, x8
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; stp x0, x1, [x7, #504]
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; ret
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function %i128_imm_offset_negative_large(i64) -> i128 {
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block0(v0: i64):
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v1 = load.i128 v0-512
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store.i128 v1, v0-512
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return v1
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}
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; block0:
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; mov x8, x0
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; mov x6, x8
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; ldp x0, x1, [x6, #-512]
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; mov x7, x8
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; stp x0, x1, [x7, #-512]
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; ret
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function %i128_add_offset(i64) -> i128 {
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block0(v0: i64):
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v1 = iadd_imm v0, 32
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v2 = load.i128 v1
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store.i128 v2, v1
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return v2
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}
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; block0:
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; mov x8, x0
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; mov x6, x8
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; ldp x0, x1, [x6, #32]
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; mov x7, x8
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; stp x0, x1, [x7, #32]
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; ret
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function %i128_32bit_sextend_simple(i32) -> i128 {
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block0(v0: i32):
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v1 = sextend.i64 v0
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v2 = load.i128 v1
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store.i128 v2, v1
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return v2
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}
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; block0:
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; sxtw x6, w0
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; ldp x10, x1, [x6]
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; sxtw x7, w0
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; mov x0, x10
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; stp x0, x1, [x7]
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; ret
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function %i128_32bit_sextend(i64, i32) -> i128 {
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block0(v0: i64, v1: i32):
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v2 = sextend.i64 v1
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v3 = iadd.i64 v0, v2
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v4 = iadd_imm.i64 v3, 24
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v5 = load.i128 v4
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store.i128 v5, v4
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return v5
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}
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; block0:
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; mov x11, x0
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; mov x7, x11
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; add x7, x7, x1, SXTW
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; ldp x0, x10, [x7, #24]
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; mov x9, x11
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; add x9, x9, x1, SXTW
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; mov x1, x10
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; stp x0, x1, [x9, #24]
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; ret
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