48573b52b2
I hadn't realized before that the filetest backend for `test vcode` is doing essentially what `compile` is doing, but for new (`MachInst`) backends: it is just getting a disassembly and running it through filecheck. There's no reason not to reuse `test compile` for the AArch64 tests as well. This was motivated by the desire to have "this IR compiles successfully" tests work on both x86 and AArch64. It seems this should work fine by adding multiple `target` directives when a test case should be compile-tested on multiple architectures.
327 lines
6.2 KiB
Plaintext
327 lines
6.2 KiB
Plaintext
test compile
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target aarch64
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function %a(i8) -> i8 {
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block0(v0: i8):
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v1 = bitrev v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: lsr w0, w0, #24
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %a(i16) -> i16 {
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block0(v0: i16):
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v1 = bitrev v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: lsr w0, w0, #16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %a(i32) -> i32 {
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block0(v0: i32):
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v1 = bitrev v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %a(i64) -> i64 {
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block0(v0: i64):
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v1 = bitrev v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit x0, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %b(i8) -> i8 {
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block0(v0: i8):
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v1 = clz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %b(i16) -> i16 {
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block0(v0: i16):
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v1 = clz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %b(i32) -> i32 {
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block0(v0: i32):
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v1 = clz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %b(i64) -> i64 {
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block0(v0: i64):
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v1 = clz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: clz x0, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %c(i8) -> i8 {
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block0(v0: i8):
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v1 = cls v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: cls w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %c(i16) -> i16 {
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block0(v0: i16):
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v1 = cls v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: cls w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %c(i32) -> i32 {
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block0(v0: i32):
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v1 = cls v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: cls w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %c(i64) -> i64 {
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block0(v0: i64):
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v1 = cls v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: cls x0, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i8) -> i8 {
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block0(v0: i8):
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v1 = ctz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: lsr w0, w0, #24
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i16) -> i16 {
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block0(v0: i16):
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v1 = ctz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: lsr w0, w0, #16
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i32) -> i32 {
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block0(v0: i32):
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v1 = ctz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit w0, w0
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; nextln: clz w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i64) -> i64 {
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block0(v0: i64):
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v1 = ctz v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: rbit x0, x0
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; nextln: clz x0, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i64) -> i64 {
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block0(v0: i64):
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v1 = popcnt v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: lsr x1, x0, #1
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; nextln: and x1, x1, #6148914691236517205
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; nextln: sub x1, x0, x1
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; nextln: and x0, x1, #3689348814741910323
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; nextln: lsr x1, x1, #2
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; nextln: and x1, x1, #3689348814741910323
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; nextln: add x0, x1, x0
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; nextln: add x0, x0, x0, LSR 4
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; nextln: and x0, x0, #1085102592571150095
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; nextln: add x0, x0, x0, LSL 8
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; nextln: add x0, x0, x0, LSL 16
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; nextln: add x0, x0, x0, LSL 32
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; nextln: lsr x0, x0, #56
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i32) -> i32 {
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block0(v0: i32):
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v1 = popcnt v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: lsr w1, w0, #1
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; nextln: and x1, x1, #6148914691236517205
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; nextln: sub x1, x0, x1
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; nextln: and x0, x1, #3689348814741910323
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; nextln: lsr x1, x1, #2
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; nextln: and x1, x1, #3689348814741910323
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; nextln: add x0, x1, x0
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; nextln: add x0, x0, x0, LSR 4
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; nextln: and x0, x0, #1085102592571150095
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; nextln: add x0, x0, x0, LSL 8
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; nextln: add x0, x0, x0, LSL 16
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; nextln: add x0, x0, x0, LSL 32
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; nextln: lsr x0, x0, #56
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i16) -> i16 {
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block0(v0: i16):
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v1 = popcnt v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth x0, w0
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; nextln: lsr w1, w0, #1
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; nextln: and x1, x1, #6148914691236517205
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; nextln: sub x1, x0, x1
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; nextln: and x0, x1, #3689348814741910323
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; nextln: lsr x1, x1, #2
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; nextln: and x1, x1, #3689348814741910323
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; nextln: add x0, x1, x0
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; nextln: add x0, x0, x0, LSR 4
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; nextln: and x0, x0, #1085102592571150095
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; nextln: add x0, x0, x0, LSL 8
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; nextln: add x0, x0, x0, LSL 16
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; nextln: add x0, x0, x0, LSL 32
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; nextln: lsr x0, x0, #56
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %d(i8) -> i8 {
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block0(v0: i8):
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v1 = popcnt v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb x0, w0
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; nextln: lsr w1, w0, #1
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; nextln: and x1, x1, #6148914691236517205
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; nextln: sub x1, x0, x1
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; nextln: and x0, x1, #3689348814741910323
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; nextln: lsr x1, x1, #2
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; nextln: and x1, x1, #3689348814741910323
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; nextln: add x0, x1, x0
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; nextln: add x0, x0, x0, LSR 4
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; nextln: and x0, x0, #1085102592571150095
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; nextln: add x0, x0, x0, LSL 8
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; nextln: add x0, x0, x0, LSL 16
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; nextln: add x0, x0, x0, LSL 32
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; nextln: lsr x0, x0, #56
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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