c5ddb4b803
* [AArch64] Port SIMD narrowing to ISLE Fvdemote, snarrow, unarrow and uunarrow. Also refactor the aarch64 instructions descriptions to parameterize on ScalarSize instead of using different opcodes. The zero_value pure constructor has been introduced and used by the integer narrow operations and it replaces, and extends, the compare zero patterns. Copright (c) 2022, Arm Limited. * use short 'if' patterns
101 lines
4.8 KiB
Common Lisp
101 lines
4.8 KiB
Common Lisp
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;;;; Rules for `iadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (iadd x y)))
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(value_reg (add_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (isub x y)))
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(value_reg (sub_vec (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `imul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (lane_fits_in_32 ty @ (dynamic_lane _ _)) (imul x y)))
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(value_reg (vec_rrr (VecALUOp.Mul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fadd` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fadd x y)))
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(value_reg (vec_rrr (VecALUOp.Fadd) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fsub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fsub x y)))
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(value_reg (vec_rrr (VecALUOp.Fsub) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fmul x y)))
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(value_reg (vec_rrr (VecALUOp.Fmul) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fdiv x y)))
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(value_reg (vec_rrr (VecALUOp.Fdiv) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fmin x y)))
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(value_reg (vec_rrr (VecALUOp.Fmin) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fmax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fmax x y)))
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(value_reg (vec_rrr (VecALUOp.Fmax) (put_in_reg x) (put_in_reg y) (vector_size ty))))
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;;;; Rules for `fmin_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fmin_pseudo x y)))
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(value_reg (bsl ty
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(vec_rrr (VecALUOp.Fcmgt) (put_in_reg x) (put_in_reg y)
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(vector_size ty)) (put_in_reg y) (put_in_reg x))))
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;;;; Rules for `fmax_pseudo` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type ty @ (dynamic_lane _ _) (fmax_pseudo x y)))
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(value_reg (bsl ty
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(vec_rrr (VecALUOp.Fcmgt) (put_in_reg y) (put_in_reg x)
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(vector_size ty)) (put_in_reg y) (put_in_reg x))))
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;;;; Rules for `snarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
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(if-let _ (zero_value y))
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(sqxtn x (lane_size ty)))
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(rule (lower (has_type (ty_dyn64_int ty) (snarrow x y)))
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(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
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(sqxtn dst (lane_size ty))))
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(rule (lower (has_type (ty_dyn128_int ty) (snarrow x y)))
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(let ((low_half Reg (sqxtn x (lane_size ty)))
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(result Reg (sqxtn2 low_half y (lane_size ty))))
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result))
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;;;; Rules for `unarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
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(if-let _ (zero_value y))
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(sqxtun x (lane_size ty)))
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(rule (lower (has_type (ty_dyn64_int ty) (unarrow x y)))
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(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
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(sqxtun dst (lane_size ty))))
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(rule (lower (has_type (ty_dyn128_int ty) (unarrow x y)))
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(let ((low_half Reg (sqxtun x (lane_size ty)))
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(result Reg (sqxtun2 low_half y (lane_size ty))))
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result))
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;;;; Rules for `uunarrow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
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(if-let _ (zero_value y))
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(uqxtn x (lane_size ty)))
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(rule (lower (has_type (ty_dyn64_int ty) (uunarrow x y)))
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(let ((dst Reg (mov_vec_elem x y 1 0 (VectorSize.Size64x2))))
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(uqxtn dst (lane_size ty))))
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(rule (lower (has_type (ty_dyn128_int ty) (uunarrow x y)))
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(let ((low_half Reg (uqxtn x (lane_size ty)))
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(result Reg (uqxtn2 low_half y (lane_size ty))))
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result))
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;;; Rules for `dynamic_stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (dynamic_stack_addr stack_slot))
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(let ((dst WritableReg (temp_writable_reg $I64))
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(_ Unit (emit (abi_dynamic_stackslot_addr dst stack_slot))))
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(value_reg dst)))
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;;; Rules for `extract_vector` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(rule (lower (extract_vector x 0))
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(value_reg (fpu_move_128 (put_in_reg x))))
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