Jakob Stoklund Olesen 247be57042 Also write out register assignments in write_instruction. ...

The value locations appear after the encodings:

> [R#0c,%x2]              v0 = iadd vx0, vx1
> [Iret#19]               return_reg v0

2017-02-22 11:53:01 -08:00

..

ir

Add assertion that the NonZero optimization works on Option<Opcode>.

2017-02-22 10:22:08 -08:00

isa

SSA register coloring pass.

2017-02-22 11:53:01 -08:00

regalloc

Add a register allocation context module.

2017-02-22 11:53:01 -08:00

cfg.rs

Make the ControlFlowGraph reusable.

2017-02-17 12:20:33 -08:00

constant_hash.rs

Speling.

2017-02-03 12:49:40 -08:00

context.rs

Add a register allocation context module.

2017-02-22 11:53:01 -08:00

dominator_tree.rs

Make the DominatorTree reusable.

2017-02-17 13:09:41 -08:00

entity_list.rs

Speling.

2017-02-03 12:49:40 -08:00

entity_map.rs

Speling.

2017-02-03 12:49:40 -08:00

legalizer.rs

Speling.

2017-02-03 12:49:40 -08:00

lib.rs

Add a compilation context struct.

2017-02-17 12:04:53 -08:00

packed_option.rs

Use PackedOption<Inst> in the dominator tree.

2017-01-19 19:44:16 -08:00

partition_slice.rs

Add a partition_slice function.

2017-02-14 10:17:24 -08:00

predicates.rs

Speling.

2017-02-03 12:49:40 -08:00

ref_slice.rs

Add a ref_slice module.

2016-11-04 12:32:09 -07:00

settings.rs

Fill in boilerplate for Intel and ARM targets.

2016-11-23 10:42:07 -08:00

sparse_map.rs

Add a contains_key method to SparseMap.

2017-02-14 16:05:54 -08:00

verifier.rs

Removed the Opcode::NotAnOpcode variant, replaced its uses with Option<Opcode>, and used the NonZero optimization to maintain the small 1-byte size of an optional Opcode.

2017-02-22 10:22:08 -08:00

write.rs

Also write out register assignments in write_instruction.

2017-02-22 11:53:01 -08:00