041fda63ac
Tabulate the Intel opcode representations and implement an OP() function which computes the encoding bits. Implement the single-byte opcode with a reg-reg ModR/M byte.
68 lines
1.9 KiB
Python
68 lines
1.9 KiB
Python
"""
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Intel Encoding recipes.
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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# from cdsl.predicates import IsSignedInt
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from base.formats import Binary
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from .registers import GPR
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# Opcode representation.
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#
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# Cretonne requires each recipe to have a single encoding size in bytes, and
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# Intel opcodes are variable length, so we use separate recipes for different
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# styles of opcodes and prefixes. The opcode format is indicated by the recipe
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# name prefix:
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#
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# <op> Op1* OP(op)
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# 0F <op> Op2* OP(op)
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# 0F 38 <op> Op3* OP38(op)
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# 0F 3A <op> Op3* OP3A(op)
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# 66 <op> Mp1* MP66(op)
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# 66 0F <op> Mp2* MP66(op)
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# 66 0F 38 <op> Mp3* MP6638(op)
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# 66 0F 3A <op> Mp3* MP663A(op)
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# F2 <op> Mp1* MPF2(op)
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# F2 0F <op> Mp2* MPF2(op)
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# F2 0F 38 <op> Mp3* MPF238(op)
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# F2 0F 3A <op> Mp3* MPF23A(op)
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# F3 <op> Mp1* MPF3(op)
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# F3 0F <op> Mp2* MPF3(op)
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# F3 0F 38 <op> Mp3* MPF338(op)
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# F3 0F 3A <op> Mp3* MPF33A(op)
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#
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# VEX/XOP and EVEX prefixes are not yet supported.
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#
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# The encoding bits are:
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#
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# 0-7: The opcode byte <op>.
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# 8-9: pp, mandatory prefix:
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# 00 none (Op*)
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# 01 66 (Mp*)
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# 10 F3 (Mp*)
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# 11 F2 (Mp*)
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# 10-11: mm, opcode map:
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# 00 <op> (Op1/Mp1)
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# 01 0F <op> (Op2/Mp2)
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# 10 0F 38 <op> (Op3/Mp3)
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# 11 0F 3A <op> (Op3/Mp3)
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# 12-14 rrr, opcode bits for the ModR/M byte for certain opcodes.
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# 15: REX.W bit (or VEX.W/E)
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#
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# There is some redundancy between bits 8-11 and the recipe names, but we have
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# enough bits, and the pp+mm format is ready for supporting VEX prefixes.
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def OP(op, pp=0, mm=0, rrr=0, w=0):
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# type: (int, int, int, int, int) -> int
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assert op <= 0xff
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assert pp <= 0b11
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assert mm <= 0b11
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assert rrr <= 0b111
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assert w <= 1
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return op | (pp << 8) | (mm << 10) | (rrr << 12) | (w << 15)
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# XX /r
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Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
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