10efe8e780
PR 2840 changed the store_spillslot routine to always store integer registers in full word size to a spill slot. However, the load_spillslot routine was not updated, which may causes the contents to be reloaded in a different type. On big-endian systems this will fetch wrong data. Fixed by using the same type override in load_spillslot.
128 lines
3.8 KiB
Plaintext
128 lines
3.8 KiB
Plaintext
test compile
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target x86_64 machinst
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;; The goal of this test is to ensure that stack spills of an integer value,
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;; which width is less than the machine word's size, cause the full word to be
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;; stored, and not only the lower bits.
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;; Because of unsigned extensions which can be transformed into simple moves,
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;; the source vreg of the extension operation can be coalesced with its
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;; destination vreg, and if it happens to be spill, then the reload may use a
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;; reload of a different, larger size.
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function %f0(i32, i32, i32) -> i64 {
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fn0 = %g(i32) -> i64
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; check: pushq %rbp
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; nextln: movq %rsp, %rbp
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; nextln: subq $$64, %rsp
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;; Stash all the callee-saved registers.
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; nextln: movq %r12, 16(%rsp)
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; nextln: movq %r13, 24(%rsp)
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; nextln: movq %r14, 32(%rsp)
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; nextln: movq %rbx, 40(%rsp)
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; nextln: movq %r15, 48(%rsp)
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block0(v0: i32, v1: i32, v2: i32):
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;; First, create enough virtual registers so that the call instructions
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;; causes at least one of them to be spilled onto the stack.
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v3 = iadd.i32 v0, v1
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v4 = iadd.i32 v1, v2
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v5 = iadd.i32 v0, v2
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v6 = iadd.i32 v3, v0
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v7 = iadd.i32 v4, v0
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v8 = iadd.i32 v5, v0
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; nextln: movq %rdi, %r12
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; nextln: addl %esi, %r12d
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; nextln: movq %rsi, %r13
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; nextln: addl %edx, %r13d
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; nextln: movq %rdi, %r14
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; nextln: addl %edx, %r14d
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; nextln: movq %r12, %rbx
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; nextln: addl %edi, %ebx
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; nextln: movq %r13, %r15
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; nextln: addl %edi, %r15d
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; nextln: movq %r14, %rsi
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;; This should be movq below, not movl.
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; nextln: movq %rsi, rsp(0 + virtual offset)
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; nextln: movq rsp(0 + virtual offset), %rsi
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; nextln: addl %edi, %esi
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;; Put an effectful instruction so that the live-ranges of the adds and
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;; uextends are split here, and to prevent the uextend to be emitted
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;; before the call. This will effectively causing the above i32 to be
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;; spilled as an i32, and not a full i64.
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v300 = call fn0(v0)
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;; This should be movq below, not movl.
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; nextln: movq %rsi, rsp(0 + virtual offset)
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; nextln: load_ext_name %g+0, %rsi
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; nextln: call *%rsi
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v31 = uextend.i64 v3
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v41 = uextend.i64 v4
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v51 = uextend.i64 v5
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v61 = uextend.i64 v6
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v71 = uextend.i64 v7
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v81 = uextend.i64 v8
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;; None of the uextends are generated here yet.
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;; At this point, I'd expect that this second call below would be not
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;; necessary, but if it is removed, the uextend is applied before the call,
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;; and the i64 is spilled (then reloaded), causing the bug to not appear. So
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;; an additional call it is!
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v100 = call fn0(v3)
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; nextln: movq %r12, %rsi
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; nextln: movq %rsi, rsp(8 + virtual offset)
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; nextln: nop len=0
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; nextln: movq %r12, %rdi
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; nextln: load_ext_name %g+0, %rsi
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; nextln: call *%rsi
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;; Cause reloads of all the values. Most are in registers, but one of them
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;; is on the stack. Make sure they're all used in the final computation.
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v101 = iadd.i64 v100, v31
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v102 = iadd.i64 v101, v41
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v103 = iadd.i64 v102, v51
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v104 = iadd.i64 v103, v61
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v105 = iadd.i64 v104, v71
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v200 = iadd.i64 v105, v81
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; nextln: movq %rax, %rsi
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; nextln: movq rsp(8 + virtual offset), %rdi
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; nextln: addq %rdi, %rsi
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; nextln: addq %r13, %rsi
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; nextln: addq %r14, %rsi
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; nextln: addq %rbx, %rsi
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; nextln: addq %r15, %rsi
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;; The reload operates on a full word, so uses movq.
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; nextln: movq rsp(0 + virtual offset), %rdi
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; nextln: addq %rdi, %rsi
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; nextln: movq %rsi, %rax
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; nextln: movq 16(%rsp), %r12
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; nextln: movq 24(%rsp), %r13
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; nextln: movq 32(%rsp), %r14
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; nextln: movq 40(%rsp), %rbx
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; nextln: movq 48(%rsp), %r15
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; nextln: addq $$64, %rsp
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return v200
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; nextln: movq %rbp, %rsp
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; nextln: popq %rbp
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; nextln: ret
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}
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