* Enable the native target by default in winch
Match cranelift-codegen's build script where if no architecture is
explicitly enabled then the host architecture is implicitly enabled.
* Refactor Cranelift's ISA builder to share more with Winch
This commit refactors the `Builder` type to have a type parameter
representing the finished ISA with Cranelift and Winch having their own
typedefs for `Builder` to represent their own builders. The intention is
to use this shared functionality to produce more shared code between the
two codegen backends.
* Moving compiler shared components to a separate crate
* Restore native flag inference in compiler building
This fixes an oversight from the previous commits to use
`cranelift-native` to infer flags for the native host when using default
settings with Wasmtime.
* Move `Compiler::page_size_align` into wasmtime-environ
The `cranelift-codegen` crate doesn't need this and winch wants the same
implementation, so shuffle it around so everyone has access to it.
* Fill out `Compiler::{flags, isa_flags}` for Winch
These are easy enough to plumb through with some shared code for
Wasmtime.
* Plumb the `is_branch_protection_enabled` flag for Winch
Just forwarding an isa-specific setting accessor.
* Moving executable creation to shared compiler crate
* Adding builder back in and removing from shared crate
* Refactoring the shared pieces for the `CompilerBuilder`
I decided to move a couple things around from Alex's initial changes.
Instead of having the shared builder do everything, I went back to
having each compiler have a distinct builder implementation. I
refactored most of the flag setting logic into a single shared location,
so we can still reduce the amount of code duplication.
With them being separate, we don't need to maintain things like
`LinkOpts` which Winch doesn't currently use. We also have an avenue to
error when certain flags are sent to Winch if we don't support them. I'm
hoping this will make things more maintainable as we build out Winch.
I'm still unsure about keeping everything shared in a single crate
(`cranelift_shared`). It's starting to feel like this crate is doing too
much, which makes it difficult to name. There does seem to be a need for
two distinct abstraction: creating the final executable and the handling
of shared/ISA flags when building the compiler. I could make them into
two separate crates, but there doesn't seem to be enough there yet to
justify it.
* Documentation updates, and renaming the finish method
* Adding back in a default temporarily to pass tests, and removing some unused imports
* Fixing winch tests with wrong method name
* Removing unused imports from codegen shared crate
* Apply documentation formatting updates
Co-authored-by: Saúl Cabrera <saulecabrera@gmail.com>
* Adding back in cranelift_native flag inferring
* Adding new shared crate to publish list
* Adding write feature to pass cargo check
---------
Co-authored-by: Alex Crichton <alex@alexcrichton.com>
Co-authored-by: Saúl Cabrera <saulecabrera@gmail.com>
408 lines
14 KiB
Rust
408 lines
14 KiB
Rust
//! Instruction Set Architectures.
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//!
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//! The `isa` module provides a `TargetIsa` trait which provides the behavior specialization needed
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//! by the ISA-independent code generator. The sub-modules of this module provide definitions for
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//! the instruction sets that Cranelift can target. Each sub-module has it's own implementation of
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//! `TargetIsa`.
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//!
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//! # Constructing a `TargetIsa` instance
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//!
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//! The target ISA is built from the following information:
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//!
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//! - The name of the target ISA as a string. Cranelift is a cross-compiler, so the ISA to target
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//! can be selected dynamically. Individual ISAs can be left out when Cranelift is compiled, so a
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//! string is used to identify the proper sub-module.
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//! - Values for settings that apply to all ISAs. This is represented by a `settings::Flags`
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//! instance.
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//! - Values for ISA-specific settings.
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//!
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//! The `isa::lookup()` function is the main entry point which returns an `isa::Builder`
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//! appropriate for the requested ISA:
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//!
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//! ```
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//! # #[macro_use] extern crate target_lexicon;
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//! use cranelift_codegen::isa;
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//! use cranelift_codegen::settings::{self, Configurable};
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//! use std::str::FromStr;
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//! use target_lexicon::Triple;
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//!
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//! let shared_builder = settings::builder();
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//! let shared_flags = settings::Flags::new(shared_builder);
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//!
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//! match isa::lookup(triple!("x86_64")) {
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//! Err(_) => {
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//! // The x86_64 target ISA is not available.
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//! }
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//! Ok(mut isa_builder) => {
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//! isa_builder.set("use_popcnt", "on");
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//! let isa = isa_builder.finish(shared_flags);
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//! }
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//! }
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//! ```
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//!
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//! The configured target ISA trait object is a `Box<TargetIsa>` which can be used for multiple
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//! concurrent function compilations.
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use crate::dominator_tree::DominatorTree;
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pub use crate::isa::call_conv::CallConv;
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use crate::flowgraph;
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use crate::ir::{self, Function};
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#[cfg(feature = "unwind")]
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use crate::isa::unwind::systemv::RegisterMappingError;
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use crate::machinst::{CompiledCode, CompiledCodeStencil, TextSectionBuilder, UnwindInfoKind};
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use crate::settings;
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use crate::settings::SetResult;
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use crate::CodegenResult;
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use alloc::{boxed::Box, sync::Arc, vec::Vec};
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use core::fmt;
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use core::fmt::{Debug, Formatter};
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use target_lexicon::{triple, Architecture, PointerWidth, Triple};
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// This module is made public here for benchmarking purposes. No guarantees are
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// made regarding API stability.
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#[cfg(feature = "x86")]
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pub mod x64;
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#[cfg(feature = "arm64")]
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pub mod aarch64;
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#[cfg(feature = "riscv64")]
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pub mod riscv64;
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#[cfg(feature = "s390x")]
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mod s390x;
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pub mod unwind;
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mod call_conv;
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/// Returns a builder that can create a corresponding `TargetIsa`
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/// or `Err(LookupError::SupportDisabled)` if not enabled.
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macro_rules! isa_builder {
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($name: ident, $cfg_terms: tt, $triple: ident) => {{
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#[cfg $cfg_terms]
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{
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Ok($name::isa_builder($triple))
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}
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#[cfg(not $cfg_terms)]
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{
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Err(LookupError::SupportDisabled)
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}
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}};
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}
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/// Look for an ISA for the given `triple`.
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/// Return a builder that can create a corresponding `TargetIsa`.
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pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
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match triple.architecture {
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Architecture::X86_64 => {
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isa_builder!(x64, (feature = "x86"), triple)
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}
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Architecture::Aarch64 { .. } => isa_builder!(aarch64, (feature = "arm64"), triple),
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Architecture::S390x { .. } => isa_builder!(s390x, (feature = "s390x"), triple),
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Architecture::Riscv64 { .. } => isa_builder!(riscv64, (feature = "riscv64"), triple),
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_ => Err(LookupError::Unsupported),
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}
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}
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/// The string names of all the supported, but possibly not enabled, architectures. The elements of
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/// this slice are suitable to be passed to the [lookup_by_name] function to obtain the default
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/// configuration for that architecture.
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pub const ALL_ARCHITECTURES: &[&str] = &["x86_64", "aarch64", "s390x", "riscv64"];
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/// Look for a supported ISA with the given `name`.
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/// Return a builder that can create a corresponding `TargetIsa`.
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pub fn lookup_by_name(name: &str) -> Result<Builder, LookupError> {
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use alloc::str::FromStr;
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lookup(triple!(name))
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}
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/// Describes reason for target lookup failure
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#[derive(PartialEq, Eq, Copy, Clone, Debug)]
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pub enum LookupError {
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/// Support for this target was disabled in the current build.
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SupportDisabled,
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/// Support for this target has not yet been implemented.
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Unsupported,
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}
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// This is manually implementing Error and Display instead of using thiserror to reduce the amount
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// of dependencies used by Cranelift.
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impl std::error::Error for LookupError {}
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impl fmt::Display for LookupError {
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fn fmt(&self, f: &mut Formatter) -> fmt::Result {
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match self {
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LookupError::SupportDisabled => write!(f, "Support for this target is disabled"),
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LookupError::Unsupported => {
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write!(f, "Support for this target has not been implemented yet")
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}
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}
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}
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}
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/// The type of a polymorphic TargetISA object which is 'static.
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pub type OwnedTargetIsa = Arc<dyn TargetIsa>;
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/// Type alias of `IsaBuilder` used for building Cranelift's ISAs.
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pub type Builder = IsaBuilder<CodegenResult<OwnedTargetIsa>>;
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/// Builder for a `TargetIsa`.
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/// Modify the ISA-specific settings before creating the `TargetIsa` trait object with `finish`.
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#[derive(Clone)]
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pub struct IsaBuilder<T> {
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triple: Triple,
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setup: settings::Builder,
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constructor: fn(Triple, settings::Flags, &settings::Builder) -> T,
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}
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impl<T> IsaBuilder<T> {
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/// Creates a new ISA-builder from its components, namely the `triple` for
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/// the ISA, the ISA-specific settings builder, and a final constructor
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/// function to generate the ISA from its components.
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pub fn new(
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triple: Triple,
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setup: settings::Builder,
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constructor: fn(Triple, settings::Flags, &settings::Builder) -> T,
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) -> Self {
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IsaBuilder {
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triple,
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setup,
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constructor,
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}
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}
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/// Gets the triple for the builder.
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pub fn triple(&self) -> &Triple {
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&self.triple
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}
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/// Iterates the available settings in the builder.
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pub fn iter(&self) -> impl Iterator<Item = settings::Setting> {
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self.setup.iter()
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}
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/// Combine the ISA-specific settings with the provided
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/// ISA-independent settings and allocate a fully configured
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/// `TargetIsa` trait object. May return an error if some of the
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/// flags are inconsistent or incompatible: for example, some
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/// platform-independent features, like general SIMD support, may
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/// need certain ISA extensions to be enabled.
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pub fn finish(&self, shared_flags: settings::Flags) -> T {
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(self.constructor)(self.triple.clone(), shared_flags, &self.setup)
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}
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}
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impl<T> settings::Configurable for IsaBuilder<T> {
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fn set(&mut self, name: &str, value: &str) -> SetResult<()> {
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self.setup.set(name, value)
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}
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fn enable(&mut self, name: &str) -> SetResult<()> {
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self.setup.enable(name)
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}
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}
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/// After determining that an instruction doesn't have an encoding, how should we proceed to
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/// legalize it?
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///
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/// The `Encodings` iterator returns a legalization function to call.
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pub type Legalize =
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fn(ir::Inst, &mut ir::Function, &mut flowgraph::ControlFlowGraph, &dyn TargetIsa) -> bool;
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/// This struct provides information that a frontend may need to know about a target to
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/// produce Cranelift IR for the target.
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#[derive(Clone, Copy, Hash)]
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pub struct TargetFrontendConfig {
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/// The default calling convention of the target.
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pub default_call_conv: CallConv,
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/// The pointer width of the target.
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pub pointer_width: PointerWidth,
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}
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impl TargetFrontendConfig {
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/// Get the pointer type of this target.
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pub fn pointer_type(self) -> ir::Type {
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ir::Type::int(self.pointer_bits() as u16).unwrap()
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}
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/// Get the width of pointers on this target, in units of bits.
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pub fn pointer_bits(self) -> u8 {
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self.pointer_width.bits()
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}
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/// Get the width of pointers on this target, in units of bytes.
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pub fn pointer_bytes(self) -> u8 {
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self.pointer_width.bytes()
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}
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}
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/// Methods that are specialized to a target ISA.
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///
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/// Implies a Display trait that shows the shared flags, as well as any ISA-specific flags.
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pub trait TargetIsa: fmt::Display + Send + Sync {
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/// Get the name of this ISA.
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fn name(&self) -> &'static str;
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/// Get the target triple that was used to make this trait object.
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fn triple(&self) -> &Triple;
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/// Get the ISA-independent flags that were used to make this trait object.
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fn flags(&self) -> &settings::Flags;
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/// Get the ISA-dependent MachineEnv for managing register allocation.
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fn machine_env(&self) -> ®alloc2::MachineEnv;
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/// Get the ISA-dependent flag values that were used to make this trait object.
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fn isa_flags(&self) -> Vec<settings::Value>;
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/// Get a flag indicating whether branch protection is enabled.
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fn is_branch_protection_enabled(&self) -> bool {
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false
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}
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/// Get the ISA-dependent maximum vector register size, in bytes.
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fn dynamic_vector_bytes(&self, dynamic_ty: ir::Type) -> u32;
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/// Compile the given function.
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fn compile_function(
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&self,
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func: &Function,
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domtree: &DominatorTree,
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want_disasm: bool,
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) -> CodegenResult<CompiledCodeStencil>;
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#[cfg(feature = "unwind")]
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/// Map a regalloc::Reg to its corresponding DWARF register.
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fn map_regalloc_reg_to_dwarf(
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&self,
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_: crate::machinst::Reg,
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) -> Result<u16, RegisterMappingError> {
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Err(RegisterMappingError::UnsupportedArchitecture)
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}
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/// IntCC condition for Unsigned Addition Overflow (Carry).
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fn unsigned_add_overflow_condition(&self) -> ir::condcodes::IntCC;
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/// Creates unwind information for the function.
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///
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/// Returns `None` if there is no unwind information for the function.
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#[cfg(feature = "unwind")]
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fn emit_unwind_info(
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&self,
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result: &CompiledCode,
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kind: UnwindInfoKind,
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) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>>;
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/// Creates a new System V Common Information Entry for the ISA.
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///
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/// Returns `None` if the ISA does not support System V unwind information.
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#[cfg(feature = "unwind")]
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fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
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// By default, an ISA cannot create a System V CIE
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None
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}
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/// Returns an object that can be used to build the text section of an
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/// executable.
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///
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/// This object will internally attempt to handle as many relocations as
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/// possible using relative calls/jumps/etc between functions.
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///
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/// The `num_labeled_funcs` argument here is the number of functions which
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/// will be "labeled" or might have calls between them, typically the number
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/// of defined functions in the object file.
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fn text_section_builder(&self, num_labeled_funcs: usize) -> Box<dyn TextSectionBuilder>;
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/// The function alignment required by this ISA.
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fn function_alignment(&self) -> u32;
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/// Create a polymorphic TargetIsa from this specific implementation.
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fn wrapped(self) -> OwnedTargetIsa
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where
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Self: Sized + 'static,
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{
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Arc::new(self)
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}
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/// Generate a `Capstone` context for disassembling bytecode for this architecture.
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#[cfg(feature = "disas")]
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fn to_capstone(&self) -> Result<capstone::Capstone, capstone::Error> {
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Err(capstone::Error::UnsupportedArch)
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}
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/// Returns whether this ISA has a native fused-multiply-and-add instruction
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/// for floats.
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///
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/// Currently this only returns false on x86 when some native features are
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/// not detected.
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fn has_native_fma(&self) -> bool;
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}
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/// Methods implemented for free for target ISA!
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impl<'a> dyn TargetIsa + 'a {
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/// Get the default calling convention of this target.
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pub fn default_call_conv(&self) -> CallConv {
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CallConv::triple_default(self.triple())
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}
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/// Get the endianness of this ISA.
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pub fn endianness(&self) -> ir::Endianness {
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match self.triple().endianness().unwrap() {
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target_lexicon::Endianness::Little => ir::Endianness::Little,
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target_lexicon::Endianness::Big => ir::Endianness::Big,
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}
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}
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/// Returns the minimum symbol alignment for this ISA.
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pub fn symbol_alignment(&self) -> u64 {
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match self.triple().architecture {
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// All symbols need to be aligned to at least 2 on s390x.
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Architecture::S390x => 2,
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_ => 1,
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}
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}
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/// Get the pointer type of this ISA.
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pub fn pointer_type(&self) -> ir::Type {
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ir::Type::int(self.pointer_bits() as u16).unwrap()
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}
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/// Get the width of pointers on this ISA.
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pub(crate) fn pointer_width(&self) -> PointerWidth {
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self.triple().pointer_width().unwrap()
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}
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/// Get the width of pointers on this ISA, in units of bits.
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pub fn pointer_bits(&self) -> u8 {
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self.pointer_width().bits()
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}
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/// Get the width of pointers on this ISA, in units of bytes.
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pub fn pointer_bytes(&self) -> u8 {
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self.pointer_width().bytes()
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}
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/// Get the information needed by frontends producing Cranelift IR.
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pub fn frontend_config(&self) -> TargetFrontendConfig {
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TargetFrontendConfig {
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default_call_conv: self.default_call_conv(),
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pointer_width: self.pointer_width(),
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}
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}
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}
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impl Debug for &dyn TargetIsa {
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fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
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write!(
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f,
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"TargetIsa {{ triple: {:?}, pointer_width: {:?}}}",
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self.triple(),
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self.pointer_width()
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)
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}
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}
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