a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
41 lines
519 B
Plaintext
41 lines
519 B
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %ireduce_128_64(i128) -> i64 {
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block0(v0: i128):
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v1 = ireduce.i64 v0
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return v1
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}
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; block0:
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; ret
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function %ireduce_128_32(i128) -> i32 {
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block0(v0: i128):
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v1 = ireduce.i32 v0
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return v1
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}
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; block0:
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; ret
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function %ireduce_128_16(i128) -> i16 {
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block0(v0: i128):
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v1 = ireduce.i16 v0
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return v1
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}
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; block0:
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; ret
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function %ireduce_128_8(i128) -> i8 {
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block0(v0: i128):
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v1 = ireduce.i8 v0
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return v1
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}
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; block0:
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; ret
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