a0318f36f0
This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
125 lines
1.8 KiB
Plaintext
125 lines
1.8 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function u0:0(i8) -> f32 {
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block0(v0: i8):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; block0:
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; uxtb w4, w0
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; ucvtf s0, w4
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; ret
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function u0:0(i8) -> f64 {
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block0(v0: i8):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; block0:
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; uxtb w4, w0
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; ucvtf d0, w4
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; ret
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function u0:0(i16) -> f32 {
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block0(v0: i16):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; block0:
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; uxth w4, w0
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; ucvtf s0, w4
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; ret
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function u0:0(i16) -> f64 {
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block0(v0: i16):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; block0:
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; uxth w4, w0
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; ucvtf d0, w4
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; ret
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function u0:0(f32) -> i8 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i8 v0
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return v1
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}
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; block0:
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; fcmp s0, s0
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; b.vc 8 ; udf
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; fmov s6, #-1
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; fcmp s0, s6
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; b.gt 8 ; udf
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; movz x10, #17280, LSL #16
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; fmov s6, w10
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; fcmp s0, s6
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; b.mi 8 ; udf
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; fcvtzu w0, s0
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; ret
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function u0:0(f64) -> i8 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i8 v0
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return v1
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}
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; block0:
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; fcmp d0, d0
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; b.vc 8 ; udf
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; fmov d6, #-1
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; fcmp d0, d6
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; b.gt 8 ; udf
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; movz x10, #16496, LSL #48
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; fmov d6, x10
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; fcmp d0, d6
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; b.mi 8 ; udf
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; fcvtzu w0, d0
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; ret
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function u0:0(f32) -> i16 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i16 v0
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return v1
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}
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; block0:
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; fcmp s0, s0
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; b.vc 8 ; udf
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; fmov s6, #-1
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; fcmp s0, s6
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; b.gt 8 ; udf
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; movz x10, #18304, LSL #16
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; fmov s6, w10
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; fcmp s0, s6
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; b.mi 8 ; udf
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; fcvtzu w0, s0
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; ret
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function u0:0(f64) -> i16 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i16 v0
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return v1
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}
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; block0:
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; fcmp d0, d0
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; b.vc 8 ; udf
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; fmov d6, #-1
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; fcmp d0, d6
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; b.gt 8 ; udf
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; movz x10, #16624, LSL #48
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; fmov d6, x10
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; fcmp d0, d6
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; b.mi 8 ; udf
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; fcvtzu w0, d0
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; ret
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