; Binary emission of 32-bit code.
test binemit
isa riscv

function RV32I() {
ebb0:
    [-,%x10]            v1 = iconst.i32 1
    [-,%x21]            v2 = iconst.i32 2

    ; Integer Register-Register Operations.
    ; add
    [-,%x7]             v10 = iadd v1, v2       ; bin: 015503b3
    [-,%x16]            v11 = iadd v2, v1       ; bin: 00aa8833
    ; sub
    [-,%x7]             v12 = isub v1, v2       ; bin: 415503b3
    [-,%x16]            v13 = isub v2, v1       ; bin: 40aa8833
    ; and
    [-,%x7]             v20 = band v1, v2       ; bin: 015573b3
    [-,%x16]            v21 = band v2, v1       ; bin: 00aaf833
    ; or
    [-,%x7]             v22 = bor v1, v2        ; bin: 015563b3
    [-,%x16]            v23 = bor v2, v1        ; bin: 00aae833
    ; xor
    [-,%x7]             v24 = bxor v1, v2       ; bin: 015543b3
    [-,%x16]            v25 = bxor v2, v1       ; bin: 00aac833
    ; sll
    [-,%x7]             v30 = ishl v1, v2       ; bin: 015513b3
    [-,%x16]            v31 = ishl v2, v1       ; bin: 00aa9833
    ; srl
    [-,%x7]             v32 = ushr v1, v2       ; bin: 015553b3
    [-,%x16]            v33 = ushr v2, v1       ; bin: 00aad833
    ; sra
    [-,%x7]             v34 = sshr v1, v2       ; bin: 415553b3
    [-,%x16]            v35 = sshr v2, v1       ; bin: 40aad833
    ; slt
    [-,%x7]             v42 = icmp slt, v1, v2  ; bin: 015523b3
    [-,%x16]            v43 = icmp slt, v2, v1  ; bin: 00aaa833
    ; sltu
    [-,%x7]             v44 = icmp ult, v1, v2  ; bin: 015533b3
    [-,%x16]            v45 = icmp ult, v2, v1  ; bin: 00aab833

    ; Integer Register-Immediate Instructions

    ; addi
    [-,%x7]     v100 = iadd_imm v1, 1000       ; bin: 3e850393
    [-,%x16]    v101 = iadd_imm v2, -905       ; bin: c77a8813
    ; andi
    [-,%x7]     v110 = band_imm v1, 1000       ; bin: 3e857393
    [-,%x16]    v111 = band_imm v2, -905       ; bin: c77af813
    ; ori
    [-,%x7]     v112 = bor_imm v1, 1000        ; bin: 3e856393
    [-,%x16]    v113 = bor_imm v2, -905        ; bin: c77ae813
    ; xori
    [-,%x7]     v114 = bxor_imm v1, 1000       ; bin: 3e854393
    [-,%x16]    v115 = bxor_imm v2, -905       ; bin: c77ac813

    ; slli
    [-,%x7]     v120 = ishl_imm v1, 31         ; bin: 01f51393
    [-,%x16]    v121 = ishl_imm v2, 8          ; bin: 008a9813
    ; srli
    [-,%x7]     v122 = ushr_imm v1, 31         ; bin: 01f55393
    [-,%x16]    v123 = ushr_imm v2, 8          ; bin: 008ad813
    ; srai
    [-,%x7]     v124 = sshr_imm v1, 31         ; bin: 41f55393
    [-,%x16]    v125 = sshr_imm v2, 8          ; bin: 408ad813

    ; slti
    [-,%x7]     v130 = icmp_imm slt, v1, 1000  ; bin: 3e852393
    [-,%x16]    v131 = icmp_imm slt, v2, -905  ; bin: c77aa813
    ; sltiu
    [-,%x7]     v132 = icmp_imm ult, v1, 1000  ; bin: 3e853393
    [-,%x16]    v133 = icmp_imm ult, v2, -905  ; bin: c77ab813

    ; lui
    [-,%x7]     v140 = iconst.i32 0x12345000            ; bin: 123453b7
    [-,%x16]    v141 = iconst.i32 0xffffffff_fedcb000   ; bin: fedcb837

    jump ebb1

    ; Control Transfer Instructions

ebb1:
    ; beq
    br_icmp eq, v1, v2, ebb0            ; bin: Branch(ebb0) 01550063
    ; bne
    br_icmp ne, v1, v2, ebb0            ; bin: Branch(ebb0) 01551063
    ; blt
    br_icmp slt, v1, v2, ebb0           ; bin: Branch(ebb0) 01554063
    ; bge
    br_icmp sge, v1, v2, ebb0           ; bin: Branch(ebb0) 01555063
    ; bltu
    br_icmp ult, v1, v2, ebb0           ; bin: Branch(ebb0) 01556063
    ; bgeu
    br_icmp uge, v1, v2, ebb0           ; bin: Branch(ebb0) 01557063

    ; beq x, %x0
    brz v1, ebb0                        ; bin: Branch(ebb0) 00050063
    ; bne x, %x0
    brnz v1, ebb0                       ; bin: Branch(ebb0) 00051063

    return
}