test regalloc
isa intel

; regex: V=v\d+
; regex: REG=%r([abcd]x|[sd]i)

; Tied operands, both are killed at instruction.
function %tied_easy() -> i32 {
ebb0:
    v0 = iconst.i32 12
    v1 = iconst.i32 13
    ; not: copy
    ; check: isub
    v2 = isub v0, v1
    return v2
}

; Fixed register constraint.
function %fixed_op() -> i32 {
ebb0:
    ; check: ,%rax]
    ; sameln: $v0 = iconst.i32 12
    v0 = iconst.i32 12
    v1 = iconst.i32 13
    ; The dynamic shift amount must be in %rcx
    ; check: regmove $v0, %rax -> %rcx
    v2 = ishl v1, v0
    return v2
}

; Fixed register constraint twice.
function %fixed_op_twice() -> i32 {
ebb0:
    ; check: ,%rax]
    ; sameln: $v0 = iconst.i32 12
    v0 = iconst.i32 12
    v1 = iconst.i32 13
    ; The dynamic shift amount must be in %rcx
    ; check: regmove $v0, %rax -> %rcx
    v2 = ishl v1, v0
    ; check: regmove $v0, %rcx -> $REG
    ; check: regmove $v2, $REG -> %rcx
    v3 = ishl v0, v2

    return v3
}