; Binary emission of 64-bit floating point code.
test binemit
set is_64bit
isa intel has_sse2

; The binary encodings can be verified with the command:
;
;   sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
;

function %F32() {
ebb0:
    [-,%r11]            v0 = iconst.i32 1
    [-,%rsi]            v1 = iconst.i32 2
    [-,%rax]            v2 = iconst.i64 11
    [-,%r14]            v3 = iconst.i64 12

    ; asm: cvtsi2ssl %r11d, %xmm5
    [-,%xmm5]           v10 = fcvt_from_sint.f32 v0             ; bin: f3 41 0f 2a eb
    ; asm: cvtsi2ssl %esi, %xmm10
    [-,%xmm10]          v11 = fcvt_from_sint.f32 v1             ; bin: f3 44 0f 2a d6

    ; asm: cvtsi2ssq %rax, %xmm5
    [-,%xmm5]           v12 = fcvt_from_sint.f32 v2             ; bin: f3 48 0f 2a e8
    ; asm: cvtsi2ssq %r14, %xmm10
    [-,%xmm10]          v13 = fcvt_from_sint.f32 v3             ; bin: f3 4d 0f 2a d6

    ; asm: cvtss2sd %xmm10, %xmm5
    [-,%xmm5]           v14 = fpromote.f64 v11                  ; bin: f3 41 0f 5a ea
    ; asm: cvtss2sd %xmm5, %xmm10
    [-,%xmm10]          v15 = fpromote.f64 v10                  ; bin: f3 44 0f 5a d5

    ; asm: movd %r11d, %xmm5
    [-,%xmm5]           v16 = bitcast.f32 v0                    ; bin: 66 41 0f 6e eb
    ; asm: movd %esi, %xmm10
    [-,%xmm10]          v17 = bitcast.f32 v1                    ; bin: 66 44 0f 6e d6

    ; asm: movd %xmm5, %ecx
    [-,%rcx]            v18 = bitcast.i32 v10                   ; bin: 66 40 0f 7e e9
    ; asm: movd %xmm10, %esi
    [-,%rsi]            v19 = bitcast.i32 v11                   ; bin: 66 44 0f 7e d6

    ; Binary arithmetic.

    ; asm: addss %xmm10, %xmm5
    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f3 41 0f 58 ea
    ; asm: addss %xmm5, %xmm10
    [-,%xmm10]          v21 = fadd v11, v10                     ; bin: f3 44 0f 58 d5

    ; asm: subss %xmm10, %xmm5
    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f3 41 0f 5c ea
    ; asm: subss %xmm5, %xmm10
    [-,%xmm10]          v23 = fsub v11, v10                     ; bin: f3 44 0f 5c d5

    ; asm: mulss %xmm10, %xmm5
    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f3 41 0f 59 ea
    ; asm: mulss %xmm5, %xmm10
    [-,%xmm10]          v25 = fmul v11, v10                     ; bin: f3 44 0f 59 d5

    ; asm: divss %xmm10, %xmm5
    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f3 41 0f 5e ea
    ; asm: divss %xmm5, %xmm10
    [-,%xmm10]          v27 = fdiv v11, v10                     ; bin: f3 44 0f 5e d5

    ; Bitwise ops.
    ; We use the *ps SSE instructions for everything because they are smaller.

    ; asm: andps %xmm10, %xmm5
    [-,%xmm5]           v30 = band v10, v11                     ; bin: 41 0f 54 ea
    ; asm: andps %xmm5, %xmm10
    [-,%xmm10]          v31 = band v11, v10                     ; bin: 44 0f 54 d5

    ; asm: andnps %xmm10, %xmm5
    [-,%xmm5]           v32 = band_not v10, v11                 ; bin: 41 0f 55 ea
    ; asm: andnps %xmm5, %xmm10
    [-,%xmm10]          v33 = band_not v11, v10                 ; bin: 44 0f 55 d5

    ; asm: orps %xmm10, %xmm5
    [-,%xmm5]           v34 = bor v10, v11                      ; bin: 41 0f 56 ea
    ; asm: orps %xmm5, %xmm10
    [-,%xmm10]          v35 = bor v11, v10                      ; bin: 44 0f 56 d5

    ; asm: xorps %xmm10, %xmm5
    [-,%xmm5]           v36 = bxor v10, v11                     ; bin: 41 0f 57 ea
    ; asm: xorps %xmm5, %xmm10
    [-,%xmm10]          v37 = bxor v11, v10                     ; bin: 44 0f 57 d5

    return
}

function %F64() {
ebb0:
    [-,%r11]            v0 = iconst.i32 1
    [-,%rsi]            v1 = iconst.i32 2
    [-,%rax]            v2 = iconst.i64 11
    [-,%r14]            v3 = iconst.i64 12

    ; asm: cvtsi2sdl %r11d, %xmm5
    [-,%xmm5]           v10 = fcvt_from_sint.f64 v0             ; bin: f2 41 0f 2a eb
    ; asm: cvtsi2sdl %esi, %xmm10
    [-,%xmm10]          v11 = fcvt_from_sint.f64 v1             ; bin: f2 44 0f 2a d6

    ; asm: cvtsi2sdq %rax, %xmm5
    [-,%xmm5]           v12 = fcvt_from_sint.f64 v2             ; bin: f2 48 0f 2a e8
    ; asm: cvtsi2sdq %r14, %xmm10
    [-,%xmm10]          v13 = fcvt_from_sint.f64 v3             ; bin: f2 4d 0f 2a d6

    ; asm: cvtsd2ss %xmm10, %xmm5
    [-,%xmm5]           v14 = fdemote.f32 v11                   ; bin: f2 41 0f 5a ea
    ; asm: cvtsd2ss %xmm5, %xmm10
    [-,%xmm10]          v15 = fdemote.f32 v10                   ; bin: f2 44 0f 5a d5

    ; asm: movq %rax, %xmm5
    [-,%xmm5]           v16 = bitcast.f64 v2                    ; bin: 66 48 0f 6e e8
    ; asm: movq %r14, %xmm10
    [-,%xmm10]          v17 = bitcast.f64 v3                    ; bin: 66 4d 0f 6e d6

    ; asm: movq %xmm5, %rcx
    [-,%rcx]            v18 = bitcast.i64 v10                   ; bin: 66 48 0f 7e e9
    ; asm: movq %xmm10, %rsi
    [-,%rsi]            v19 = bitcast.i64 v11                   ; bin: 66 4c 0f 7e d6

    ; Binary arithmetic.

    ; asm: addsd %xmm10, %xmm5
    [-,%xmm5]           v20 = fadd v10, v11                     ; bin: f2 41 0f 58 ea
    ; asm: addsd %xmm5, %xmm10
    [-,%xmm10]          v21 = fadd v11, v10                     ; bin: f2 44 0f 58 d5

    ; asm: subsd %xmm10, %xmm5
    [-,%xmm5]           v22 = fsub v10, v11                     ; bin: f2 41 0f 5c ea
    ; asm: subsd %xmm5, %xmm10
    [-,%xmm10]          v23 = fsub v11, v10                     ; bin: f2 44 0f 5c d5

    ; asm: mulsd %xmm10, %xmm5
    [-,%xmm5]           v24 = fmul v10, v11                     ; bin: f2 41 0f 59 ea
    ; asm: mulsd %xmm5, %xmm10
    [-,%xmm10]          v25 = fmul v11, v10                     ; bin: f2 44 0f 59 d5

    ; asm: divsd %xmm10, %xmm5
    [-,%xmm5]           v26 = fdiv v10, v11                     ; bin: f2 41 0f 5e ea
    ; asm: divsd %xmm5, %xmm10
    [-,%xmm10]          v27 = fdiv v11, v10                     ; bin: f2 44 0f 5e d5

    ; Bitwise ops.
    ; We use the *ps SSE instructions for everything because they are smaller.

    ; asm: andps %xmm10, %xmm5
    [-,%xmm5]           v30 = band v10, v11                     ; bin: 41 0f 54 ea
    ; asm: andps %xmm5, %xmm10
    [-,%xmm10]          v31 = band v11, v10                     ; bin: 44 0f 54 d5

    ; asm: andnps %xmm10, %xmm5
    [-,%xmm5]           v32 = band_not v10, v11                 ; bin: 41 0f 55 ea
    ; asm: andnps %xmm5, %xmm10
    [-,%xmm10]          v33 = band_not v11, v10                 ; bin: 44 0f 55 d5

    ; asm: orps %xmm10, %xmm5
    [-,%xmm5]           v34 = bor v10, v11                      ; bin: 41 0f 56 ea
    ; asm: orps %xmm5, %xmm10
    [-,%xmm10]          v35 = bor v11, v10                      ; bin: 44 0f 56 d5

    ; asm: xorps %xmm10, %xmm5
    [-,%xmm5]           v36 = bxor v10, v11                     ; bin: 41 0f 57 ea
    ; asm: xorps %xmm5, %xmm10
    [-,%xmm10]          v37 = bxor v11, v10                     ; bin: 44 0f 57 d5

    return
}