test compile precise-output
target aarch64

function %swidenhigh_i8x16(i8) -> i16x8 {
  gv0 = dyn_scale_target_const.i16x8
  gv1 = dyn_scale_target_const.i8x16
  dt0 = i8x16*gv1
  dt1 = i16x8*gv0

block0(v0: i8):
  v1 = splat.dt0 v0
  v2 = swiden_high v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.16b, w0
;   sxtl2 v0.8h, v3.16b
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.16b, w0
;   sshll2 v0.8h, v3.16b, #0
;   ret

function %swidenhigh_i16x8(i16) -> i32x4 {
  gv0 = dyn_scale_target_const.i32x4
  gv1 = dyn_scale_target_const.i16x8
  dt0 = i16x8*gv1
  dt1 = i32x4*gv0

block0(v0: i16):
  v1 = splat.dt0 v0
  v2 = swiden_high v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.8h, w0
;   sxtl2 v0.4s, v3.8h
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.8h, w0
;   sshll2 v0.4s, v3.8h, #0
;   ret

function %swidenhigh_i32x4(i32) -> i64x2 {
  gv0 = dyn_scale_target_const.i32x4
  gv1 = dyn_scale_target_const.i64x2
  dt0 = i64x2*gv1
  dt1 = i32x4*gv0

block0(v0: i32):
  v1 = splat.dt1 v0
  v2 = swiden_high v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.4s, w0
;   sxtl2 v0.2d, v3.4s
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.4s, w0
;   sshll2 v0.2d, v3.4s, #0
;   ret

function %swidenlow_i8x16(i8) -> i16x8 {
  gv0 = dyn_scale_target_const.i16x8
  gv1 = dyn_scale_target_const.i8x16
  dt0 = i8x16*gv1
  dt1 = i16x8*gv0

block0(v0: i8):
  v1 = splat.dt0 v0
  v2 = swiden_low v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.16b, w0
;   sxtl v0.8h, v3.8b
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.16b, w0
;   sshll v0.8h, v3.8b, #0
;   ret

function %swidenlow_i16x8(i16) -> i32x4 {
  gv0 = dyn_scale_target_const.i32x4
  gv1 = dyn_scale_target_const.i16x8
  dt0 = i16x8*gv1
  dt1 = i32x4*gv0

block0(v0: i16):
  v1 = splat.dt0 v0
  v2 = swiden_low v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.8h, w0
;   sxtl v0.4s, v3.4h
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.8h, w0
;   sshll v0.4s, v3.4h, #0
;   ret

function %swidenlow_i32x4(i32) -> i64x2 {
  gv0 = dyn_scale_target_const.i32x4
  gv1 = dyn_scale_target_const.i64x2
  dt0 = i64x2*gv1
  dt1 = i32x4*gv0

block0(v0: i32):
  v1 = splat.dt1 v0
  v2 = swiden_low v1
  v3 = extract_vector v2, 0
  return v3
}

; VCode:
; block0:
;   dup v3.4s, w0
;   sxtl v0.2d, v3.2s
;   ret
; 
; Disassembled:
; block0: ; offset 0x0
;   dup v3.4s, w0
;   sshll v0.2d, v3.2s, #0
;   ret