; binary emission of x86-32 code. test binemit set opt_level=best target i686 haswell ; The binary encodings can be verified with the command: ; ; sed -ne 's/^ *; asm: *//p' filetests/isa/x86/binary32.cton | llvm-mc -show-encoding -triple=i386 ; function %I32() { sig0 = () fn0 = %foo() gv0 = globalsym %some_gv ss0 = incoming_arg 8, offset 0 ss1 = incoming_arg 1024, offset -1024 ss2 = incoming_arg 1024, offset -2048 ss3 = incoming_arg 8, offset -2056 ebb0: ; asm: movl $1, %ecx [-,%rcx] v1 = iconst.i32 1 ; bin: b9 00000001 ; asm: movl $2, %esi [-,%rsi] v2 = iconst.i32 2 ; bin: be 00000002 ; asm: movb $1, %cl [-,%rcx] v9007 = bconst.b1 true ; bin: b9 00000001 ; Integer Register-Register Operations. ; asm: addl %esi, %ecx [-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1 ; asm: addl %ecx, %esi [-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce ; asm: subl %esi, %ecx [-,%rcx] v12 = isub v1, v2 ; bin: 29 f1 ; asm: subl %ecx, %esi [-,%rsi] v13 = isub v2, v1 ; bin: 29 ce ; asm: andl %esi, %ecx [-,%rcx] v14 = band v1, v2 ; bin: 21 f1 ; asm: andl %ecx, %esi [-,%rsi] v15 = band v2, v1 ; bin: 21 ce ; asm: orl %esi, %ecx [-,%rcx] v16 = bor v1, v2 ; bin: 09 f1 ; asm: orl %ecx, %esi [-,%rsi] v17 = bor v2, v1 ; bin: 09 ce ; asm: xorl %esi, %ecx [-,%rcx] v18 = bxor v1, v2 ; bin: 31 f1 ; asm: xorl %ecx, %esi [-,%rsi] v19 = bxor v2, v1 ; bin: 31 ce ; Dynamic shifts take the shift amount in %rcx. ; asm: shll %cl, %esi [-,%rsi] v20 = ishl v2, v1 ; bin: d3 e6 ; asm: shll %cl, %ecx [-,%rcx] v21 = ishl v1, v1 ; bin: d3 e1 ; asm: shrl %cl, %esi [-,%rsi] v22 = ushr v2, v1 ; bin: d3 ee ; asm: shrl %cl, %ecx [-,%rcx] v23 = ushr v1, v1 ; bin: d3 e9 ; asm: sarl %cl, %esi [-,%rsi] v24 = sshr v2, v1 ; bin: d3 fe ; asm: sarl %cl, %ecx [-,%rcx] v25 = sshr v1, v1 ; bin: d3 f9 ; asm: roll %cl, %esi [-,%rsi] v26 = rotl v2, v1 ; bin: d3 c6 ; asm: roll %cl, %ecx [-,%rcx] v27 = rotl v1, v1 ; bin: d3 c1 ; asm: rorl %cl, %esi [-,%rsi] v28 = rotr v2, v1 ; bin: d3 ce ; asm: rorl %cl, %ecx [-,%rcx] v29 = rotr v1, v1 ; bin: d3 c9 ; Integer Register - Immediate 8-bit operations. ; The 8-bit immediate is sign-extended. ; asm: addl $-128, %ecx [-,%rcx] v30 = iadd_imm v1, -128 ; bin: 83 c1 80 ; asm: addl $10, %esi [-,%rsi] v31 = iadd_imm v2, 10 ; bin: 83 c6 0a ; asm: andl $-128, %ecx [-,%rcx] v32 = band_imm v1, -128 ; bin: 83 e1 80 ; asm: andl $10, %esi [-,%rsi] v33 = band_imm v2, 10 ; bin: 83 e6 0a ; asm: orl $-128, %ecx [-,%rcx] v34 = bor_imm v1, -128 ; bin: 83 c9 80 ; asm: orl $10, %esi [-,%rsi] v35 = bor_imm v2, 10 ; bin: 83 ce 0a ; asm: xorl $-128, %ecx [-,%rcx] v36 = bxor_imm v1, -128 ; bin: 83 f1 80 ; asm: xorl $10, %esi [-,%rsi] v37 = bxor_imm v2, 10 ; bin: 83 f6 0a ; Integer Register - Immediate 32-bit operations. ; asm: addl $-128000, %ecx [-,%rcx] v40 = iadd_imm v1, -128000 ; bin: 81 c1 fffe0c00 ; asm: addl $1000000, %esi [-,%rsi] v41 = iadd_imm v2, 1000000 ; bin: 81 c6 000f4240 ; asm: andl $-128000, %ecx [-,%rcx] v42 = band_imm v1, -128000 ; bin: 81 e1 fffe0c00 ; asm: andl $1000000, %esi [-,%rsi] v43 = band_imm v2, 1000000 ; bin: 81 e6 000f4240 ; asm: orl $-128000, %ecx [-,%rcx] v44 = bor_imm v1, -128000 ; bin: 81 c9 fffe0c00 ; asm: orl $1000000, %esi [-,%rsi] v45 = bor_imm v2, 1000000 ; bin: 81 ce 000f4240 ; asm: xorl $-128000, %ecx [-,%rcx] v46 = bxor_imm v1, -128000 ; bin: 81 f1 fffe0c00 ; asm: xorl $1000000, %esi [-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240 ; More arithmetic. ; asm: imull %esi, %ecx [-,%rcx] v50 = imul v1, v2 ; bin: 0f af ce ; asm: imull %ecx, %esi [-,%rsi] v51 = imul v2, v1 ; bin: 0f af f1 ; asm: movl $1, %eax [-,%rax] v52 = iconst.i32 1 ; bin: b8 00000001 ; asm: movl $2, %edx [-,%rdx] v53 = iconst.i32 2 ; bin: ba 00000002 ; asm: idivl %ecx [-,%rax,%rdx] v54, v55 = x86_sdivmodx v52, v53, v1 ; bin: int_divz f7 f9 ; asm: idivl %esi [-,%rax,%rdx] v56, v57 = x86_sdivmodx v52, v53, v2 ; bin: int_divz f7 fe ; asm: divl %ecx [-,%rax,%rdx] v58, v59 = x86_udivmodx v52, v53, v1 ; bin: int_divz f7 f1 ; asm: divl %esi [-,%rax,%rdx] v60, v61 = x86_udivmodx v52, v53, v2 ; bin: int_divz f7 f6 ; Register copies. ; asm: movl %esi, %ecx [-,%rcx] v80 = copy v2 ; bin: 89 f1 ; asm: movl %ecx, %esi [-,%rsi] v81 = copy v1 ; bin: 89 ce ; Copy Special ; asm: movl %esp, %ebp copy_special %rsp -> %rbp ; bin: 89 e5 ; asm: movl %ebp, %esp copy_special %rbp -> %rsp ; bin: 89 ec ; Load/Store instructions. ; Register indirect addressing with no displacement. ; asm: movl %ecx, (%esi) store v1, v2 ; bin: heap_oob 89 0e ; asm: movl %esi, (%ecx) store v2, v1 ; bin: heap_oob 89 31 ; asm: movw %cx, (%esi) istore16 v1, v2 ; bin: heap_oob 66 89 0e ; asm: movw %si, (%ecx) istore16 v2, v1 ; bin: heap_oob 66 89 31 ; asm: movb %cl, (%esi) istore8 v1, v2 ; bin: heap_oob 88 0e ; Can't store %sil in 32-bit mode (needs REX prefix). ; asm: movl (%ecx), %edi [-,%rdi] v100 = load.i32 v1 ; bin: heap_oob 8b 39 ; asm: movl (%esi), %edx [-,%rdx] v101 = load.i32 v2 ; bin: heap_oob 8b 16 ; asm: movzwl (%ecx), %edi [-,%rdi] v102 = uload16.i32 v1 ; bin: heap_oob 0f b7 39 ; asm: movzwl (%esi), %edx [-,%rdx] v103 = uload16.i32 v2 ; bin: heap_oob 0f b7 16 ; asm: movswl (%ecx), %edi [-,%rdi] v104 = sload16.i32 v1 ; bin: heap_oob 0f bf 39 ; asm: movswl (%esi), %edx [-,%rdx] v105 = sload16.i32 v2 ; bin: heap_oob 0f bf 16 ; asm: movzbl (%ecx), %edi [-,%rdi] v106 = uload8.i32 v1 ; bin: heap_oob 0f b6 39 ; asm: movzbl (%esi), %edx [-,%rdx] v107 = uload8.i32 v2 ; bin: heap_oob 0f b6 16 ; asm: movsbl (%ecx), %edi [-,%rdi] v108 = sload8.i32 v1 ; bin: heap_oob 0f be 39 ; asm: movsbl (%esi), %edx [-,%rdx] v109 = sload8.i32 v2 ; bin: heap_oob 0f be 16 ; Register-indirect with 8-bit signed displacement. ; asm: movl %ecx, 100(%esi) store v1, v2+100 ; bin: heap_oob 89 4e 64 ; asm: movl %esi, -100(%ecx) store v2, v1-100 ; bin: heap_oob 89 71 9c ; asm: movw %cx, 100(%esi) istore16 v1, v2+100 ; bin: heap_oob 66 89 4e 64 ; asm: movw %si, -100(%ecx) istore16 v2, v1-100 ; bin: heap_oob 66 89 71 9c ; asm: movb %cl, 100(%esi) istore8 v1, v2+100 ; bin: heap_oob 88 4e 64 ; asm: movl 50(%ecx), %edi [-,%rdi] v110 = load.i32 v1+50 ; bin: heap_oob 8b 79 32 ; asm: movl -50(%esi), %edx [-,%rdx] v111 = load.i32 v2-50 ; bin: heap_oob 8b 56 ce ; asm: movzwl 50(%ecx), %edi [-,%rdi] v112 = uload16.i32 v1+50 ; bin: heap_oob 0f b7 79 32 ; asm: movzwl -50(%esi), %edx [-,%rdx] v113 = uload16.i32 v2-50 ; bin: heap_oob 0f b7 56 ce ; asm: movswl 50(%ecx), %edi [-,%rdi] v114 = sload16.i32 v1+50 ; bin: heap_oob 0f bf 79 32 ; asm: movswl -50(%esi), %edx [-,%rdx] v115 = sload16.i32 v2-50 ; bin: heap_oob 0f bf 56 ce ; asm: movzbl 50(%ecx), %edi [-,%rdi] v116 = uload8.i32 v1+50 ; bin: heap_oob 0f b6 79 32 ; asm: movzbl -50(%esi), %edx [-,%rdx] v117 = uload8.i32 v2-50 ; bin: heap_oob 0f b6 56 ce ; asm: movsbl 50(%ecx), %edi [-,%rdi] v118 = sload8.i32 v1+50 ; bin: heap_oob 0f be 79 32 ; asm: movsbl -50(%esi), %edx [-,%rdx] v119 = sload8.i32 v2-50 ; bin: heap_oob 0f be 56 ce ; Register-indirect with 32-bit signed displacement. ; asm: movl %ecx, 10000(%esi) store v1, v2+10000 ; bin: heap_oob 89 8e 00002710 ; asm: movl %esi, -10000(%ecx) store v2, v1-10000 ; bin: heap_oob 89 b1 ffffd8f0 ; asm: movw %cx, 10000(%esi) istore16 v1, v2+10000 ; bin: heap_oob 66 89 8e 00002710 ; asm: movw %si, -10000(%ecx) istore16 v2, v1-10000 ; bin: heap_oob 66 89 b1 ffffd8f0 ; asm: movb %cl, 10000(%esi) istore8 v1, v2+10000 ; bin: heap_oob 88 8e 00002710 ; asm: movl 50000(%ecx), %edi [-,%rdi] v120 = load.i32 v1+50000 ; bin: heap_oob 8b b9 0000c350 ; asm: movl -50000(%esi), %edx [-,%rdx] v121 = load.i32 v2-50000 ; bin: heap_oob 8b 96 ffff3cb0 ; asm: movzwl 50000(%ecx), %edi [-,%rdi] v122 = uload16.i32 v1+50000 ; bin: heap_oob 0f b7 b9 0000c350 ; asm: movzwl -50000(%esi), %edx [-,%rdx] v123 = uload16.i32 v2-50000 ; bin: heap_oob 0f b7 96 ffff3cb0 ; asm: movswl 50000(%ecx), %edi [-,%rdi] v124 = sload16.i32 v1+50000 ; bin: heap_oob 0f bf b9 0000c350 ; asm: movswl -50000(%esi), %edx [-,%rdx] v125 = sload16.i32 v2-50000 ; bin: heap_oob 0f bf 96 ffff3cb0 ; asm: movzbl 50000(%ecx), %edi [-,%rdi] v126 = uload8.i32 v1+50000 ; bin: heap_oob 0f b6 b9 0000c350 ; asm: movzbl -50000(%esi), %edx [-,%rdx] v127 = uload8.i32 v2-50000 ; bin: heap_oob 0f b6 96 ffff3cb0 ; asm: movsbl 50000(%ecx), %edi [-,%rdi] v128 = sload8.i32 v1+50000 ; bin: heap_oob 0f be b9 0000c350 ; asm: movsbl -50000(%esi), %edx [-,%rdx] v129 = sload8.i32 v2-50000 ; bin: heap_oob 0f be 96 ffff3cb0 ; Bit-counting instructions. ; asm: popcntl %esi, %ecx [-,%rcx] v200 = popcnt v2 ; bin: f3 0f b8 ce ; asm: popcntl %ecx, %esi [-,%rsi] v201 = popcnt v1 ; bin: f3 0f b8 f1 ; asm: lzcntl %esi, %ecx [-,%rcx] v202 = clz v2 ; bin: f3 0f bd ce ; asm: lzcntl %ecx, %esi [-,%rsi] v203 = clz v1 ; bin: f3 0f bd f1 ; asm: tzcntl %esi, %ecx [-,%rcx] v204 = ctz v2 ; bin: f3 0f bc ce ; asm: tzcntl %ecx, %esi [-,%rsi] v205 = ctz v1 ; bin: f3 0f bc f1 ; Integer comparisons. ; asm: cmpl %esi, %ecx ; asm: sete %bl [-,%rbx] v300 = icmp eq v1, v2 ; bin: 39 f1 0f 94 c3 ; asm: cmpl %ecx, %esi ; asm: sete %dl [-,%rdx] v301 = icmp eq v2, v1 ; bin: 39 ce 0f 94 c2 ; asm: cmpl %esi, %ecx ; asm: setne %bl [-,%rbx] v302 = icmp ne v1, v2 ; bin: 39 f1 0f 95 c3 ; asm: cmpl %ecx, %esi ; asm: setne %dl [-,%rdx] v303 = icmp ne v2, v1 ; bin: 39 ce 0f 95 c2 ; asm: cmpl %esi, %ecx ; asm: setl %bl [-,%rbx] v304 = icmp slt v1, v2 ; bin: 39 f1 0f 9c c3 ; asm: cmpl %ecx, %esi ; asm: setl %dl [-,%rdx] v305 = icmp slt v2, v1 ; bin: 39 ce 0f 9c c2 ; asm: cmpl %esi, %ecx ; asm: setge %bl [-,%rbx] v306 = icmp sge v1, v2 ; bin: 39 f1 0f 9d c3 ; asm: cmpl %ecx, %esi ; asm: setge %dl [-,%rdx] v307 = icmp sge v2, v1 ; bin: 39 ce 0f 9d c2 ; asm: cmpl %esi, %ecx ; asm: setg %bl [-,%rbx] v308 = icmp sgt v1, v2 ; bin: 39 f1 0f 9f c3 ; asm: cmpl %ecx, %esi ; asm: setg %dl [-,%rdx] v309 = icmp sgt v2, v1 ; bin: 39 ce 0f 9f c2 ; asm: cmpl %esi, %ecx ; asm: setle %bl [-,%rbx] v310 = icmp sle v1, v2 ; bin: 39 f1 0f 9e c3 ; asm: cmpl %ecx, %esi ; asm: setle %dl [-,%rdx] v311 = icmp sle v2, v1 ; bin: 39 ce 0f 9e c2 ; asm: cmpl %esi, %ecx ; asm: setb %bl [-,%rbx] v312 = icmp ult v1, v2 ; bin: 39 f1 0f 92 c3 ; asm: cmpl %ecx, %esi ; asm: setb %dl [-,%rdx] v313 = icmp ult v2, v1 ; bin: 39 ce 0f 92 c2 ; asm: cmpl %esi, %ecx ; asm: setae %bl [-,%rbx] v314 = icmp uge v1, v2 ; bin: 39 f1 0f 93 c3 ; asm: cmpl %ecx, %esi ; asm: setae %dl [-,%rdx] v315 = icmp uge v2, v1 ; bin: 39 ce 0f 93 c2 ; asm: cmpl %esi, %ecx ; asm: seta %bl [-,%rbx] v316 = icmp ugt v1, v2 ; bin: 39 f1 0f 97 c3 ; asm: cmpl %ecx, %esi ; asm: seta %dl [-,%rdx] v317 = icmp ugt v2, v1 ; bin: 39 ce 0f 97 c2 ; asm: cmpl %esi, %ecx ; asm: setbe %bl [-,%rbx] v318 = icmp ule v1, v2 ; bin: 39 f1 0f 96 c3 ; asm: cmpl %ecx, %esi ; asm: setbe %dl [-,%rdx] v319 = icmp ule v2, v1 ; bin: 39 ce 0f 96 c2 ; Bool-to-int conversions. ; asm: movzbl %bl, %ecx [-,%rcx] v350 = bint.i32 v300 ; bin: 0f b6 cb ; asm: movzbl %dl, %esi [-,%rsi] v351 = bint.i32 v301 ; bin: 0f b6 f2 ; asm: call foo call fn0() ; bin: stk_ovf e8 PCRel4(%foo-4) 00000000 ; asm: movl $0, %ecx [-,%rcx] v400 = func_addr.i32 fn0 ; bin: b9 Abs4(%foo) 00000000 ; asm: movl $0, %esi [-,%rsi] v401 = func_addr.i32 fn0 ; bin: be Abs4(%foo) 00000000 ; asm: call *%ecx call_indirect sig0, v400() ; bin: stk_ovf ff d1 ; asm: call *%esi call_indirect sig0, v401() ; bin: stk_ovf ff d6 ; asm: movl $0, %ecx [-,%rcx] v450 = globalsym_addr.i32 gv0 ; bin: b9 Abs4(%some_gv) 00000000 ; asm: movl $0, %esi [-,%rsi] v451 = globalsym_addr.i32 gv0 ; bin: be Abs4(%some_gv) 00000000 ; Spill / Fill. ; asm: movl %ecx, 1032(%esp) [-,ss1] v500 = spill v1 ; bin: stk_ovf 89 8c 24 00000408 ; asm: movl %esi, 1032(%esp) [-,ss1] v501 = spill v2 ; bin: stk_ovf 89 b4 24 00000408 ; asm: movl 1032(%esp), %ecx [-,%rcx] v510 = fill v500 ; bin: stk_ovf 8b 8c 24 00000408 ; asm: movl 1032(%esp), %esi [-,%rsi] v511 = fill v501 ; bin: stk_ovf 8b b4 24 00000408 ; asm: movl %ecx, 1032(%esp) regspill v1, %rcx -> ss1 ; bin: stk_ovf 89 8c 24 00000408 ; asm: movl 1032(%esp), %ecx regfill v1, ss1 -> %rcx ; bin: stk_ovf 8b 8c 24 00000408 ; Push and Pop ; asm: pushl %ecx x86_push v1 ; bin: stk_ovf 51 ; asm: popl %ecx [-,%rcx] v512 = x86_pop.i32 ; bin: stk_ovf 59 ; Adjust Stack Pointer Up ; asm: addl $64, %esp adjust_sp_up_imm 64 ; bin: 83 c4 40 ; asm: addl $-64, %esp adjust_sp_up_imm -64 ; bin: 83 c4 c0 ; asm: addl $1024, %esp adjust_sp_up_imm 1024 ; bin: 81 c4 00000400 ; asm: addl $-1024, %esp adjust_sp_up_imm -1024 ; bin: 81 c4 fffffc00 ; asm: addl $2147483647, %esp adjust_sp_up_imm 2147483647 ; bin: 81 c4 7fffffff ; asm: addl $-2147483648, %esp adjust_sp_up_imm -2147483648 ; bin: 81 c4 80000000 ; Adjust Stack Pointer Down ; asm: subl %ecx, %esp adjust_sp_down v1 ; bin: 29 cc ; asm: subl %esi, %esp adjust_sp_down v2 ; bin: 29 f4 ; asm: addl $64, %esp adjust_sp_down_imm 64 ; bin: 83 ec 40 ; asm: addl $-64, %esp adjust_sp_down_imm -64 ; bin: 83 ec c0 ; asm: addl $1024, %esp adjust_sp_down_imm 1024 ; bin: 81 ec 00000400 ; asm: addl $-1024, %esp adjust_sp_down_imm -1024 ; bin: 81 ec fffffc00 ; asm: addl $2147483647, %esp adjust_sp_down_imm 2147483647 ; bin: 81 ec 7fffffff ; asm: addl $-2147483648, %esp adjust_sp_down_imm -2147483648 ; bin: 81 ec 80000000 ; Shift immediates ; asm: shll $2, %esi [-,%rsi] v513 = ishl_imm v2, 2 ; bin: c1 e6 02 ; asm: sarl $5, %esi [-,%rsi] v514 = sshr_imm v2, 5 ; bin: c1 fe 05 ; asm: shrl $8, %esi [-,%rsi] v515 = ushr_imm v2, 8 ; bin: c1 ee 08 ; Load Complex [-,%rax] v521 = iconst.i32 1 [-,%rbx] v522 = iconst.i32 1 ; asm: movl (%eax,%ebx,1), %ecx [-,%rcx] v526 = load_complex.i32 v521+v522 ; bin: heap_oob 8b 0c 18 ; asm: movl 1(%eax,%ebx,1), %ecx [-,%rcx] v528 = load_complex.i32 v521+v522+1 ; bin: heap_oob 8b 4c 18 01 ; asm: mov 0x100000(%eax,%ebx,1),%ecx [-,%rcx] v530 = load_complex.i32 v521+v522+0x1000 ; bin: heap_oob 8b 8c 18 00001000 ; asm: movzbl (%eax,%ebx,1),%ecx [-,%rcx] v532 = uload8_complex.i32 v521+v522 ; bin: heap_oob 0f b6 0c 18 ; asm: movsbl (%eax,%ebx,1),%ecx [-,%rcx] v534 = sload8_complex.i32 v521+v522 ; bin: heap_oob 0f be 0c 18 ; asm: movzwl (%eax,%ebx,1),%ecx [-,%rcx] v536 = uload16_complex.i32 v521+v522 ; bin: heap_oob 0f b7 0c 18 ; asm: movswl (%eax,%ebx,1),%ecx [-,%rcx] v538 = sload16_complex.i32 v521+v522 ; bin: heap_oob 0f bf 0c 18 ; Store Complex [-,%rcx] v601 = iconst.i32 1 ; asm: mov %ecx,(%eax,%ebx,1) store_complex v601, v521+v522 ; bin: heap_oob 89 0c 18 ; asm: mov %ecx,0x1(%eax,%ebx,1) store_complex v601, v521+v522+1 ; bin: heap_oob 89 4c 18 01 ; asm: mov %ecx,0x100000(%eax,%ebx,1) store_complex v601, v521+v522+0x1000 ; bin: heap_oob 89 8c 18 00001000 ; asm: mov %cx,(%eax,%ebx,1) istore16_complex v601, v521+v522 ; bin: heap_oob 66 89 0c 18 ; asm: mov %cl,(%eax,%ebx,1) istore8_complex v601, v521+v522 ; bin: heap_oob 88 0c 18 ; asm: testl %ecx, %ecx ; asm: je ebb1 brz v1, ebb1 ; bin: 85 c9 74 0e ; asm: testl %esi, %esi ; asm: je ebb1 brz v2, ebb1 ; bin: 85 f6 74 0a ; asm: testl %ecx, %ecx ; asm: jne ebb1 brnz v1, ebb1 ; bin: 85 c9 75 06 ; asm: testl %esi, %esi ; asm: jne ebb1 brnz v2, ebb1 ; bin: 85 f6 75 02 ; asm: jmp ebb2 jump ebb2 ; bin: eb 01 ; asm: ebb1: ebb1: ; asm: ret return ; bin: c3 ; asm: ebb2: ebb2: trap user0 ; bin: user0 0f 0b } ; Special branch encodings only for I32 mode. function %special_branches() { ebb0: [-,%rcx] v1 = iconst.i32 1 [-,%rsi] v2 = iconst.i32 2 [-,%rdi] v3 = icmp eq v1, v2 [-,%rbx] v4 = icmp ugt v1, v2 ; asm: testl $0xff, %edi ; asm: je ebb1 brz v3, ebb1 ; bin: f7 c7 000000ff 0f 84 00000015 ; asm: testb %bl, %bl ; asm: je ebb1 brz v4, ebb1 ; bin: 84 db 74 11 ; asm: testl $0xff, %edi ; asm: jne ebb1 brnz v3, ebb1 ; bin: f7 c7 000000ff 0f 85 00000005 ; asm: testb %bl, %bl ; asm: jne ebb1 brnz v4, ebb1 ; bin: 84 db 75 01 return ebb1: return } ; CPU flag instructions. function %cpu_flags() { ebb0: [-,%rcx] v1 = iconst.i32 1 [-,%rsi] v2 = iconst.i32 2 jump ebb1 ebb1: ; asm: cmpl %esi, %ecx [-,%rflags] v10 = ifcmp v1, v2 ; bin: 39 f1 ; asm: cmpl %ecx, %esi [-,%rflags] v11 = ifcmp v2, v1 ; bin: 39 ce ; asm: je ebb1 brif eq v11, ebb1 ; bin: 74 fa ; asm: jne ebb1 brif ne v11, ebb1 ; bin: 75 f8 ; asm: jl ebb1 brif slt v11, ebb1 ; bin: 7c f6 ; asm: jge ebb1 brif sge v11, ebb1 ; bin: 7d f4 ; asm: jg ebb1 brif sgt v11, ebb1 ; bin: 7f f2 ; asm: jle ebb1 brif sle v11, ebb1 ; bin: 7e f0 ; asm: jb ebb1 brif ult v11, ebb1 ; bin: 72 ee ; asm: jae ebb1 brif uge v11, ebb1 ; bin: 73 ec ; asm: ja ebb1 brif ugt v11, ebb1 ; bin: 77 ea ; asm: jbe ebb1 brif ule v11, ebb1 ; bin: 76 e8 ; asm: sete %bl [-,%rbx] v20 = trueif eq v11 ; bin: 0f 94 c3 ; asm: setne %bl [-,%rbx] v21 = trueif ne v11 ; bin: 0f 95 c3 ; asm: setl %dl [-,%rdx] v22 = trueif slt v11 ; bin: 0f 9c c2 ; asm: setge %dl [-,%rdx] v23 = trueif sge v11 ; bin: 0f 9d c2 ; asm: setg %bl [-,%rbx] v24 = trueif sgt v11 ; bin: 0f 9f c3 ; asm: setle %bl [-,%rbx] v25 = trueif sle v11 ; bin: 0f 9e c3 ; asm: setb %dl [-,%rdx] v26 = trueif ult v11 ; bin: 0f 92 c2 ; asm: setae %dl [-,%rdx] v27 = trueif uge v11 ; bin: 0f 93 c2 ; asm: seta %bl [-,%rbx] v28 = trueif ugt v11 ; bin: 0f 97 c3 ; asm: setbe %bl [-,%rbx] v29 = trueif ule v11 ; bin: 0f 96 c3 ; The trapif instructions are encoded as macros: a conditional jump over a ud2. ; asm: jne .+4; ud2 trapif eq v11, user0 ; bin: 75 02 user0 0f 0b ; asm: je .+4; ud2 trapif ne v11, user0 ; bin: 74 02 user0 0f 0b ; asm: jnl .+4; ud2 trapif slt v11, user0 ; bin: 7d 02 user0 0f 0b ; asm: jnge .+4; ud2 trapif sge v11, user0 ; bin: 7c 02 user0 0f 0b ; asm: jng .+4; ud2 trapif sgt v11, user0 ; bin: 7e 02 user0 0f 0b ; asm: jnle .+4; ud2 trapif sle v11, user0 ; bin: 7f 02 user0 0f 0b ; asm: jnb .+4; ud2 trapif ult v11, user0 ; bin: 73 02 user0 0f 0b ; asm: jnae .+4; ud2 trapif uge v11, user0 ; bin: 72 02 user0 0f 0b ; asm: jna .+4; ud2 trapif ugt v11, user0 ; bin: 76 02 user0 0f 0b ; asm: jnbe .+4; ud2 trapif ule v11, user0 ; bin: 77 02 user0 0f 0b ; Stack check. ; asm: cmpl %esp, %ecx [-,%rflags] v40 = ifcmp_sp v1 ; bin: 39 e1 ; asm: cmpl %esp, %esi [-,%rflags] v41 = ifcmp_sp v2 ; bin: 39 e6 ; asm: cmpl $-100, %ecx [-,%rflags] v42 = ifcmp_imm v1, -100 ; bin: 83 f9 9c ; asm: cmpl $100, %esi [-,%rflags] v43 = ifcmp_imm v2, 100 ; bin: 83 fe 64 ; asm: cmpl $-10000, %ecx [-,%rflags] v44 = ifcmp_imm v1, -10000 ; bin: 81 f9 ffffd8f0 ; asm: cmpl $10000, %esi [-,%rflags] v45 = ifcmp_imm v2, 10000 ; bin: 81 fe 00002710 return } ; Tests for i32/i8 conversion instructions. function %I32_I8() { ebb0: [-,%rcx] v1 = iconst.i32 1 [-,%rcx] v11 = ireduce.i8 v1 ; bin: ; asm: movsbl %cl, %esi [-,%rsi] v20 = sextend.i32 v11 ; bin: 0f be f1 ; asm: movzbl %cl, %esi [-,%rsi] v30 = uextend.i32 v11 ; bin: 0f b6 f1 trap user0 ; bin: user0 0f 0b } ; Tests for i32/i16 conversion instructions. function %I32_I16() { ebb0: [-,%rcx] v1 = iconst.i32 1 [-,%rcx] v11 = ireduce.i16 v1 ; bin: ; asm: movswl %cx, %esi [-,%rsi] v20 = sextend.i32 v11 ; bin: 0f bf f1 ; asm: movzwl %cx, %esi [-,%rsi] v30 = uextend.i32 v11 ; bin: 0f b7 f1 trap user0 ; bin: user0 0f 0b }