; binary emission of 64-bit code. test binemit set is_64bit isa intel haswell ; The binary encodings can be verified with the command: ; ; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64.cton | llvm-mc -show-encoding -triple=x86_64 ; ; Tests for i64 instructions. function %I64() { fn0 = function %foo() sig0 = signature() ebb0: ; Integer Constants. ; asm: movq $0x01020304f1f2f3f4, %rcx [-,%rcx] v1 = iconst.i64 0x0102_0304_f1f2_f3f4 ; bin: 48 b9 01020304f1f2f3f4 ; asm: movq $0x11020304f1f2f3f4, %rsi [-,%rsi] v2 = iconst.i64 0x1102_0304_f1f2_f3f4 ; bin: 48 be 11020304f1f2f3f4 ; asm: movq $0x21020304f1f2f3f4, %r10 [-,%r10] v3 = iconst.i64 0x2102_0304_f1f2_f3f4 ; bin: 49 ba 21020304f1f2f3f4 ; asm: movl $0xff001122, %r8d # 32-bit zero-extended constant. [-,%r8] v4 = iconst.i64 0xff00_1122 ; bin: 41 b8 ff001122 ; asm: movq $0xffffffff88001122, %r14 # 32-bit sign-extended constant. [-,%r14] v5 = iconst.i64 0xffff_ffff_8800_1122 ; bin: 49 c7 c6 88001122 ; Integer Register-Register Operations. ; asm: addq %rsi, %rcx [-,%rcx] v10 = iadd v1, v2 ; bin: 48 01 f1 ; asm: addq %r10, %rsi [-,%rsi] v11 = iadd v2, v3 ; bin: 4c 01 d6 ; asm: addq %rcx, %r10 [-,%r10] v12 = iadd v3, v1 ; bin: 49 01 ca ; asm: subq %rsi, %rcx [-,%rcx] v20 = isub v1, v2 ; bin: 48 29 f1 ; asm: subq %r10, %rsi [-,%rsi] v21 = isub v2, v3 ; bin: 4c 29 d6 ; asm: subq %rcx, %r10 [-,%r10] v22 = isub v3, v1 ; bin: 49 29 ca ; asm: andq %rsi, %rcx [-,%rcx] v30 = band v1, v2 ; bin: 48 21 f1 ; asm: andq %r10, %rsi [-,%rsi] v31 = band v2, v3 ; bin: 4c 21 d6 ; asm: andq %rcx, %r10 [-,%r10] v32 = band v3, v1 ; bin: 49 21 ca ; asm: orq %rsi, %rcx [-,%rcx] v40 = bor v1, v2 ; bin: 48 09 f1 ; asm: orq %r10, %rsi [-,%rsi] v41 = bor v2, v3 ; bin: 4c 09 d6 ; asm: orq %rcx, %r10 [-,%r10] v42 = bor v3, v1 ; bin: 49 09 ca ; asm: xorq %rsi, %rcx [-,%rcx] v50 = bxor v1, v2 ; bin: 48 31 f1 ; asm: xorq %r10, %rsi [-,%rsi] v51 = bxor v2, v3 ; bin: 4c 31 d6 ; asm: xorq %rcx, %r10 [-,%r10] v52 = bxor v3, v1 ; bin: 49 31 ca ; asm: shlq %cl, %rsi [-,%rsi] v60 = ishl v2, v1 ; bin: 48 d3 e6 ; asm: shlq %cl, %r10 [-,%r10] v61 = ishl v3, v1 ; bin: 49 d3 e2 ; asm: sarq %cl, %rsi [-,%rsi] v62 = sshr v2, v1 ; bin: 48 d3 fe ; asm: sarq %cl, %r10 [-,%r10] v63 = sshr v3, v1 ; bin: 49 d3 fa ; asm: shrq %cl, %rsi [-,%rsi] v64 = ushr v2, v1 ; bin: 48 d3 ee ; asm: shrq %cl, %r10 [-,%r10] v65 = ushr v3, v1 ; bin: 49 d3 ea ; asm: rolq %cl, %rsi [-,%rsi] v66 = rotl v2, v1 ; bin: 48 d3 c6 ; asm: rolq %cl, %r10 [-,%r10] v67 = rotl v3, v1 ; bin: 49 d3 c2 ; asm: rorq %cl, %rsi [-,%rsi] v68 = rotr v2, v1 ; bin: 48 d3 ce ; asm: rorq %cl, %r10 [-,%r10] v69 = rotr v3, v1 ; bin: 49 d3 ca ; Integer Register-Immediate Operations. ; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits. ; Some take 8-bit immediates that are sign-extended to 64 bits. ; asm: addq $-100000, %rcx [-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 48 81 c1 fffe7960 ; asm: addq $100000, %rsi [-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 48 81 c6 000186a0 ; asm: addq $0x7fffffff, %r10 [-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 49 81 c2 7fffffff ; asm: addq $100, %r8 [-,%r8] v73 = iadd_imm v4, 100 ; bin: 49 83 c0 64 ; asm: addq $-100, %r14 [-,%r14] v74 = iadd_imm v5, -100 ; bin: 49 83 c6 9c ; asm: andq $-100000, %rcx [-,%rcx] v80 = band_imm v1, -100000 ; bin: 48 81 e1 fffe7960 ; asm: andq $100000, %rsi [-,%rsi] v81 = band_imm v2, 100000 ; bin: 48 81 e6 000186a0 ; asm: andq $0x7fffffff, %r10 [-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 49 81 e2 7fffffff ; asm: andq $100, %r8 [-,%r8] v83 = band_imm v4, 100 ; bin: 49 83 e0 64 ; asm: andq $-100, %r14 [-,%r14] v84 = band_imm v5, -100 ; bin: 49 83 e6 9c ; asm: orq $-100000, %rcx [-,%rcx] v90 = bor_imm v1, -100000 ; bin: 48 81 c9 fffe7960 ; asm: orq $100000, %rsi [-,%rsi] v91 = bor_imm v2, 100000 ; bin: 48 81 ce 000186a0 ; asm: orq $0x7fffffff, %r10 [-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 49 81 ca 7fffffff ; asm: orq $100, %r8 [-,%r8] v93 = bor_imm v4, 100 ; bin: 49 83 c8 64 ; asm: orq $-100, %r14 [-,%r14] v94 = bor_imm v5, -100 ; bin: 49 83 ce 9c ; asm: ret ; asm: xorq $-100000, %rcx [-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 48 81 f1 fffe7960 ; asm: xorq $100000, %rsi [-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 48 81 f6 000186a0 ; asm: xorq $0x7fffffff, %r10 [-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 49 81 f2 7fffffff ; asm: xorq $100, %r8 [-,%r8] v103 = bxor_imm v4, 100 ; bin: 49 83 f0 64 ; asm: xorq $-100, %r14 [-,%r14] v104 = bxor_imm v5, -100 ; bin: 49 83 f6 9c ; Register copies. ; asm: movq %rsi, %rcx [-,%rcx] v110 = copy v2 ; bin: 48 89 f1 ; asm: movq %r10, %rsi [-,%rsi] v111 = copy v3 ; bin: 4c 89 d6 ; asm: movq %rcx, %r10 [-,%r10] v112 = copy v1 ; bin: 49 89 ca ; More arithmetic. ; asm: imulq %rsi, %rcx [-,%rcx] v120 = imul v1, v2 ; bin: 48 0f af ce ; asm: imulq %r10, %rsi [-,%rsi] v121 = imul v2, v3 ; bin: 49 0f af f2 ; asm: imulq %rcx, %r10 [-,%r10] v122 = imul v3, v1 ; bin: 4c 0f af d1 [-,%rax] v130 = iconst.i64 1 [-,%rdx] v131 = iconst.i64 2 ; asm: idivq %rcx [-,%rax,%rdx] v132, v133 = x86_sdivmodx v130, v131, v1 ; bin: 48 f7 f9 ; asm: idivq %rsi [-,%rax,%rdx] v134, v135 = x86_sdivmodx v130, v131, v2 ; bin: 48 f7 fe ; asm: idivq %r10 [-,%rax,%rdx] v136, v137 = x86_sdivmodx v130, v131, v3 ; bin: 49 f7 fa ; asm: divq %rcx [-,%rax,%rdx] v138, v139 = x86_udivmodx v130, v131, v1 ; bin: 48 f7 f1 ; asm: divq %rsi [-,%rax,%rdx] v140, v141 = x86_udivmodx v130, v131, v2 ; bin: 48 f7 f6 ; asm: divq %r10 [-,%rax,%rdx] v142, v143 = x86_udivmodx v130, v131, v3 ; bin: 49 f7 f2 ; Bit-counting instructions. ; asm: popcntq %rsi, %rcx [-,%rcx] v200 = popcnt v2 ; bin: f3 48 0f b8 ce ; asm: popcntq %r10, %rsi [-,%rsi] v201 = popcnt v3 ; bin: f3 49 0f b8 f2 ; asm: popcntq %rcx, %r10 [-,%r10] v202 = popcnt v1 ; bin: f3 4c 0f b8 d1 ; asm: lzcntq %rsi, %rcx [-,%rcx] v203 = clz v2 ; bin: f3 48 0f bd ce ; asm: lzcntq %r10, %rsi [-,%rsi] v204 = clz v3 ; bin: f3 49 0f bd f2 ; asm: lzcntq %rcx, %r10 [-,%r10] v205 = clz v1 ; bin: f3 4c 0f bd d1 ; asm: tzcntq %rsi, %rcx [-,%rcx] v206 = ctz v2 ; bin: f3 48 0f bc ce ; asm: tzcntq %r10, %rsi [-,%rsi] v207 = ctz v3 ; bin: f3 49 0f bc f2 ; asm: tzcntq %rcx, %r10 [-,%r10] v208 = ctz v1 ; bin: f3 4c 0f bc d1 return ; bin: c3 } ; Tests for i32 instructions in 64-bit mode. ; ; Note that many i32 instructions can be encoded both with and without a REX ; prefix if they only use the low 8 registers. Here, we are testing the REX ; encodings which are chosen by default. Switching to non-REX encodings should ; be done by an instruction shrinking pass. function %I32() { fn0 = function %foo() sig0 = signature() ebb0: ; Integer Constants. ; asm: movl $0x01020304, %ecx [-,%rcx] v1 = iconst.i32 0x0102_0304 ; bin: 40 b9 01020304 ; asm: movl $0x11020304, %esi [-,%rsi] v2 = iconst.i32 0x1102_0304 ; bin: 40 be 11020304 ; asm: movl $0x21020304, %r10d [-,%r10] v3 = iconst.i32 0x2102_0304 ; bin: 41 ba 21020304 ; asm: movl $0xff001122, %r8d [-,%r8] v4 = iconst.i32 0xff00_1122 ; bin: 41 b8 ff001122 ; asm: movl $0x88001122, %r14d [-,%r14] v5 = iconst.i32 0xffff_ffff_8800_1122 ; bin: 41 be 88001122 ; Integer Register-Register Operations. ; asm: addl %esi, %ecx [-,%rcx] v10 = iadd v1, v2 ; bin: 40 01 f1 ; asm: addl %r10d, %esi [-,%rsi] v11 = iadd v2, v3 ; bin: 44 01 d6 ; asm: addl %ecx, %r10d [-,%r10] v12 = iadd v3, v1 ; bin: 41 01 ca ; asm: subl %esi, %ecx [-,%rcx] v20 = isub v1, v2 ; bin: 40 29 f1 ; asm: subl %r10d, %esi [-,%rsi] v21 = isub v2, v3 ; bin: 44 29 d6 ; asm: subl %ecx, %r10d [-,%r10] v22 = isub v3, v1 ; bin: 41 29 ca ; asm: andl %esi, %ecx [-,%rcx] v30 = band v1, v2 ; bin: 40 21 f1 ; asm: andl %r10d, %esi [-,%rsi] v31 = band v2, v3 ; bin: 44 21 d6 ; asm: andl %ecx, %r10d [-,%r10] v32 = band v3, v1 ; bin: 41 21 ca ; asm: orl %esi, %ecx [-,%rcx] v40 = bor v1, v2 ; bin: 40 09 f1 ; asm: orl %r10d, %esi [-,%rsi] v41 = bor v2, v3 ; bin: 44 09 d6 ; asm: orl %ecx, %r10d [-,%r10] v42 = bor v3, v1 ; bin: 41 09 ca ; asm: xorl %esi, %ecx [-,%rcx] v50 = bxor v1, v2 ; bin: 40 31 f1 ; asm: xorl %r10d, %esi [-,%rsi] v51 = bxor v2, v3 ; bin: 44 31 d6 ; asm: xorl %ecx, %r10d [-,%r10] v52 = bxor v3, v1 ; bin: 41 31 ca ; asm: shll %cl, %esi [-,%rsi] v60 = ishl v2, v1 ; bin: 40 d3 e6 ; asm: shll %cl, %r10d [-,%r10] v61 = ishl v3, v1 ; bin: 41 d3 e2 ; asm: sarl %cl, %esi [-,%rsi] v62 = sshr v2, v1 ; bin: 40 d3 fe ; asm: sarl %cl, %r10d [-,%r10] v63 = sshr v3, v1 ; bin: 41 d3 fa ; asm: shrl %cl, %esi [-,%rsi] v64 = ushr v2, v1 ; bin: 40 d3 ee ; asm: shrl %cl, %r10d [-,%r10] v65 = ushr v3, v1 ; bin: 41 d3 ea ; asm: roll %cl, %esi [-,%rsi] v66 = rotl v2, v1 ; bin: 40 d3 c6 ; asm: roll %cl, %r10d [-,%r10] v67 = rotl v3, v1 ; bin: 41 d3 c2 ; asm: rorl %cl, %esi [-,%rsi] v68 = rotr v2, v1 ; bin: 40 d3 ce ; asm: rorl %cl, %r10d [-,%r10] v69 = rotr v3, v1 ; bin: 41 d3 ca ; Integer Register-Immediate Operations. ; These 64-bit ops all use a 32-bit immediate that is sign-extended to 64 bits. ; Some take 8-bit immediates that are sign-extended to 64 bits. ; asm: addl $-100000, %ecx [-,%rcx] v70 = iadd_imm v1, -100000 ; bin: 40 81 c1 fffe7960 ; asm: addl $100000, %esi [-,%rsi] v71 = iadd_imm v2, 100000 ; bin: 40 81 c6 000186a0 ; asm: addl $0x7fffffff, %r10d [-,%r10] v72 = iadd_imm v3, 0x7fff_ffff ; bin: 41 81 c2 7fffffff ; asm: addl $100, %r8d [-,%r8] v73 = iadd_imm v4, 100 ; bin: 41 83 c0 64 ; asm: addl $-100, %r14d [-,%r14] v74 = iadd_imm v5, -100 ; bin: 41 83 c6 9c ; asm: andl $-100000, %ecx [-,%rcx] v80 = band_imm v1, -100000 ; bin: 40 81 e1 fffe7960 ; asm: andl $100000, %esi [-,%rsi] v81 = band_imm v2, 100000 ; bin: 40 81 e6 000186a0 ; asm: andl $0x7fffffff, %r10d [-,%r10] v82 = band_imm v3, 0x7fff_ffff ; bin: 41 81 e2 7fffffff ; asm: andl $100, %r8d [-,%r8] v83 = band_imm v4, 100 ; bin: 41 83 e0 64 ; asm: andl $-100, %r14d [-,%r14] v84 = band_imm v5, -100 ; bin: 41 83 e6 9c ; asm: orl $-100000, %ecx [-,%rcx] v90 = bor_imm v1, -100000 ; bin: 40 81 c9 fffe7960 ; asm: orl $100000, %esi [-,%rsi] v91 = bor_imm v2, 100000 ; bin: 40 81 ce 000186a0 ; asm: orl $0x7fffffff, %r10d [-,%r10] v92 = bor_imm v3, 0x7fff_ffff ; bin: 41 81 ca 7fffffff ; asm: orl $100, %r8d [-,%r8] v93 = bor_imm v4, 100 ; bin: 41 83 c8 64 ; asm: orl $-100, %r14d [-,%r14] v94 = bor_imm v5, -100 ; bin: 41 83 ce 9c ; asm: ret ; asm: xorl $-100000, %ecx [-,%rcx] v100 = bxor_imm v1, -100000 ; bin: 40 81 f1 fffe7960 ; asm: xorl $100000, %esi [-,%rsi] v101 = bxor_imm v2, 100000 ; bin: 40 81 f6 000186a0 ; asm: xorl $0x7fffffff, %r10d [-,%r10] v102 = bxor_imm v3, 0x7fff_ffff ; bin: 41 81 f2 7fffffff ; asm: xorl $100, %r8d [-,%r8] v103 = bxor_imm v4, 100 ; bin: 41 83 f0 64 ; asm: xorl $-100, %r14d [-,%r14] v104 = bxor_imm v5, -100 ; bin: 41 83 f6 9c ; Register copies. ; asm: movl %esi, %ecx [-,%rcx] v110 = copy v2 ; bin: 40 89 f1 ; asm: movl %r10d, %esi [-,%rsi] v111 = copy v3 ; bin: 44 89 d6 ; asm: movl %ecx, %r10d [-,%r10] v112 = copy v1 ; bin: 41 89 ca ; More arithmetic. ; asm: imull %esi, %ecx [-,%rcx] v120 = imul v1, v2 ; bin: 40 0f af ce ; asm: imull %r10d, %esi [-,%rsi] v121 = imul v2, v3 ; bin: 41 0f af f2 ; asm: imull %ecx, %r10d [-,%r10] v122 = imul v3, v1 ; bin: 44 0f af d1 [-,%rax] v130 = iconst.i32 1 [-,%rdx] v131 = iconst.i32 2 ; asm: idivl %rcx [-,%rax,%rdx] v132, v133 = x86_sdivmodx v130, v131, v1 ; bin: 40 f7 f9 ; asm: idivl %rsi [-,%rax,%rdx] v134, v135 = x86_sdivmodx v130, v131, v2 ; bin: 40 f7 fe ; asm: idivl %r10d [-,%rax,%rdx] v136, v137 = x86_sdivmodx v130, v131, v3 ; bin: 41 f7 fa ; asm: divl %rcx [-,%rax,%rdx] v138, v139 = x86_udivmodx v130, v131, v1 ; bin: 40 f7 f1 ; asm: divl %rsi [-,%rax,%rdx] v140, v141 = x86_udivmodx v130, v131, v2 ; bin: 40 f7 f6 ; asm: divl %r10d [-,%rax,%rdx] v142, v143 = x86_udivmodx v130, v131, v3 ; bin: 41 f7 f2 ; Bit-counting instructions. ; asm: popcntl %esi, %ecx [-,%rcx] v200 = popcnt v2 ; bin: f3 40 0f b8 ce ; asm: popcntl %r10d, %esi [-,%rsi] v201 = popcnt v3 ; bin: f3 41 0f b8 f2 ; asm: popcntl %ecx, %r10d [-,%r10] v202 = popcnt v1 ; bin: f3 44 0f b8 d1 ; asm: lzcntl %esi, %ecx [-,%rcx] v203 = clz v2 ; bin: f3 40 0f bd ce ; asm: lzcntl %r10d, %esi [-,%rsi] v204 = clz v3 ; bin: f3 41 0f bd f2 ; asm: lzcntl %ecx, %r10d [-,%r10] v205 = clz v1 ; bin: f3 44 0f bd d1 ; asm: tzcntl %esi, %ecx [-,%rcx] v206 = ctz v2 ; bin: f3 40 0f bc ce ; asm: tzcntl %r10d, %esi [-,%rsi] v207 = ctz v3 ; bin: f3 41 0f bc f2 ; asm: tzcntl %ecx, %r10d [-,%r10] v208 = ctz v1 ; bin: f3 44 0f bc d1 return ; bin: c3 }